Embedded Networking and Communications

In this week we are assigned to design, build, and connect wired or wireless node(s) with network or bus addresses as an individual assignment. In this assignment I used I2C wired communication protocol

Communication Between two microcontrollers

I2C (Inter Integrated Circuit)

I2C (Inter Integrated Circuit) is serial bus interface connection protocol. It uses only two wires for communication, that two wires called as SDA (serial data) and SCL (serial clock). It is half duplex serial communication protocol and works with multi masters and multi slaves for short distance intra-board communication. Masters are the nodes that generate clock signal and initiate communication. Slaves are the nodes that recieve the clock and respond when addressed by masters.

Task Requirments

Two micro controllers, master(ATmega 328p) and slave(ATtiny 44)

Jumper wires

Laptop

Task Procedure

Since it is not possible to use SDA and SCL pins of my board, I used to download TinyWire library which provides I2C support for ATtiny micro controllers and have only a Universal Serial Interface and copythe file and paste it in arduino libraries file. We are going to switch On/Off of the slave micro controllerLED by the command from the master microcontroller

Atmega 328/P (Master)

Since we are using Atmega 328P, the hardware support 7 bit address which equal 128 address and that means you can use 128 device from 0 to 127 on the I2C bus. Standard clock speed are 100 Khz and 10 Khz but the standard let you use clock speed from 0 to 100 Khz and the fast mode is 400 Khz and even higher speed 3.4 Mhz. After reading ATmega 328 P data sheet about 2 wire serial interface I found the following features :

Full duplex operation (independent serial receive and transmit registers)

Asynchronous or synchronous operation

Master or slave clocked synchronous operation

High resolution baud rate generator

Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

Odd or even parity generation and parity check supported by hardware

Data overrun detection

Framing error detection

Noise filtering includes false start bit detection and digital low pass filter

Three separate interrupts on TX complete, TX data register empty and RX complete

Multi-processor communication mode

Double speed asynchronous communication mode

The code

As we said previously that the Masters are the nodes that generate clock signal and initiate communication. We chose the SCL pin = A2 while the SCL port = Port C and SDA pin = 13 and SDA port = Port B.