A tightly optimized hardware-firmware vertical architecture engineered for the Digital Contour Gauge.
## Research and Introduction
The Digital Contour Guage project comes from my personal experience and encounters where utilizing a simple tool can enhance engineering
workflows , and the current solutions provided to date do not tackle directly creating a robust solution to acheive that, more details can be found
on my [final project](../final-project.html) page.
For this week I tried to define the system integrations and identify early on issues before production, to which I arrived to the summarized conclustions
1) My DFM checklist:
- 3D Modeled parts with minimal overhangs and supports , optimized files (70%)
- Defining BOM and off the shelf materials to avoid external depencancy or custom made parts (80%)
- Fastner reduction and elimination of threaded assemblies (50%)
- Alternative parts and spare parts availability (70%)
2) My overall design progress
-conceptual design phase (100%)
-preliminary design phase (40%)
-Detailed final design (5%)
3)
Preliminary 3D Model
## Design approach
I have been familiar to work with the design thinking approach in my experience so I followed through it , to summ it up:
Define : Transform the mechanical contour guage into a fully working intelligent and digital version
Ideate : Integrate slide motion along with a custom built potentiometer and CAD softwares to extract contour profiles
### Prototype Development Roadmap
The prototyping phase is summarized below, establishing targeted goals to evaluate different system modules:
| Cycle | Prototyping Objectives | Status / Scope |
| :--- | :--- | :--- |
| **Prototype 1** | Evaluate mechanical tolerances, structural integrity, hardness, and surface finish of 3D-printed chassis components. | **Completed** |
| **Prototype 2** | Test fundamental electronic hardware and map the initial design for a custom milled PCB integrating multiplexers and high-impedance potentiometer nodes. | **In Progress** |
| **Prototype 3** | Formulate a physical Proof of Concept (POC) to test mechanical alignment and structural fitment between sliding tines and the central electronic assembly. | **Planned** |
| **Prototype 4** | Build and test Version 1 of the custom sensor array stackup to benchmark voltage distribution. | **Planned** |
| **Prototype 5** | Establish a functional Proof of Concept for the localized user interface screen rendering and downstream hardware communication architecture. | **Planned** |
### Design Progression
* **Conceptual:** Making a Proof of Concept for the electronics part and the main assembly of the digital contour guage,integrating them into a simple mockup and a test canvas to iterate over for the preliminary design.
* **Preliminary:** The preliminary design is in the 3D modelling phase.
* **Detailed:** Detailed subassembly designs are stil in the CAD phase
### BOM
The Bill of Materials for the components needed so far can be found in the table below:
| Subsystem | Component Description | Qty | Notes / Specifications |
| :--- | :--- | :--- | :--- |
| **Core Electronics** | Seeed Studio XIAO RP2040 (or ESP32C3) | 1 | High-performance main MCU |
| | CD74HC4067 16-Channel Multiplexer | 2 | Handles 32 analog channels sequentially |
| | 0.96” OLED Display Module (SSD1306) | 1 | 128x64 resolution, 4-pin I2C interface |
| **Sensor Stackup** | Milled FR1 Single-Sided Copper Board | 1 | Base stator containing 32 vertical traces |
| | Velostat Conductive Plastic Sheet | 1 | Solid resistive layer for voltage division |
| | Brass or Copper Busbars | 2 | Distributes 5V and GND along Velostat edges |
| **Mechanicals** | Custom Sliding Tines | 32 | FDM 3D printed (PLA) with 1.5mm fillets |
| | Steel Rollers / Miniature Bearings | 32 | Mounted on tines as electrical wiper contacts |
| | Main Enclosure Chassis | 1 | FDM 3D printed structured outer housing |
| **Hardware / Fixes**| Brass Heat-Set Inserts | Multiple | Melted into plastic to prevent stripped threads |
| | M2 External Screws | Multiple | For housing assembly and busbar tracking |
| | Loctite 242 Threadlocker | 1 | Applied to metal fasteners to resist vibration |
| **Passives & Wiring**| 0.1µF Ceramic Capacitors | 2 | Decoupling capacitors for power stability |
| | 10kΩ Resistors | 2 | Pull-down resistors for multiplexer SIG lines |
| | 4.7kΩ Resistors | 2 | Pull-up resistors for I2C communication lines |
| | 2.54mm Female Junction Headers | 2 Rows | Board-to-board connections and MCU docking |
### Under Study BOM Items
| Category / Item | Component Specification | Application / Design Role | Compatibility Notes |
| :--- | :--- | :--- | :--- |
| **Resistive Material** | Velostat Sheet (0.1 mm thickness) | Main continuous linear potentiometer layer for voltage division. | Needs flat, unwrinkled physical clamping. |
| **Alternative Filament** | Conductive PLA Filament | 3D printing alternative wiper tips or tines to achieve electrical continuity without metal rollers. | High internal resistance; requires software calibration adjustments. |
| **SMD Board Components**| 0805 Surface Mount Packages | 0.1µF caps, 10 kΩ pull-down, and 4.7 kΩ pull-up resistors for custom milled PCB. | Optimized for manual reflow soldering or hot-plate production. |
| **Battery (XIAO ESP32C3)**| 3.7V LiPo Battery (500–1000 mAh) | Portable power source utilizing the board's built-in charging circuit. | Connects directly to the native battery pads underneath the MCU. |
| **Battery (XIAO RP2040)**| 3.7V LiPo Battery + External TP4056 Charger | Portable power assembly requiring an external charging module. | Requires regulation or connection via the VCC/GND pins as it lacks native charge circuitry. |
| **Alternative Display** | 1.3” or 2.4” ST7789 / ILI9341 SPI TFT | Higher resolution color screen option replacing the monochrome 0.96” I2C OLED. | Requires SPI routing (MOSI, CLK, CS, DC, RST) and a dedicated PWM pin for backlight control. |
## Architectural Structural Hierarchy
The assembly framework is entirely divided into specialized functional structural blocks engineered to mirror and validate one another:
This structural module runs on two distinct tracking substrate scenarios detailed in the grid layout below.
Scenario A: Flexible Velostat sheet material acting as a continuous linear pressure potentiometer.
Scenario B: 3D-printed conductive carbon tracks serving as native sliding guides and signal paths.
### Sub-Assembly Breakdown
* **Main Assembly:** The unified tool enclosure bringing together and securing the matching dual-sensor structural board stackup.
* **Sub-Assembly 2 (The Tine Array):** Tight-fit sliding pins tracking edge-to-edge, populated with low-friction steel roller bearings serving as local electrical bridge points.
* **Sub-Assembly 3 (Front Sensor & Logic Frame):** House frame containing multiplexers, interface guide walls, the OLED display, and the interface button.
* **Sub-Assembly 4 (Electronic Module Casing):** A custom protective cover preventing internal dirt or particulate contamination.
* **Sub-Assembly 5 (The Dual-PCB Substrate):** Milled single-sided copper FR1 laminates designed explicitly to align face-to-face and complement each other to close the tracking loop.
## Packaging & Spatial Packaging
### Fasteners & Alignment Mechanics
* **Standoff Elimination:** Traditional nylon standoffs are to be completely replaced by tight sliding channel tracks integrated directly within the internal perimeter walls of the plastic enclosure shell.
* **Wire Routing & Fatigue Elimination:** **Zero moving internal wiring.** All sensor signals bridge directly via physical steel rolling contacts running on stationary tracks.
* **Tine Alignment:** The pins are positioned closely next to each other. By filling the fixed housing width perfectly, the elements apply natural sideways compression against one another to clear alignment play. When using *Conductive Filament*, the printed paths natively double as integrated tracking rails.
### Tactile Surface Finish
Surface resolution parameters are dictated strictly by FDM manufacturing constraints. Friction performance and sliding coefficients are explicitly tuned using calculated layer heights ($0.2\text{mm}$) and specific nozzle geometries ($0.4\text{mm}$).
## Testing, Diagnostics & Failure Analysis
### Quality Protocols
* **QA (Defect Prevention):** Enforced electronic clearance boundaries inside the KiCAD layout file and oversampling software routines to eliminate noise harmonics.
* **QC (Defect Detection):** Hardware multi-point terminal checks with a digital multimeter paired with sequential software diagnostic script checks.
### Stress Bounds & Mitigation Strategy (FMEA)
* **Elastic Over-Extension:** An internal structural end-stop lip blocks tines from slipping completely out of the frame.
* **Stress Splitting:** 0.3-1.5mm internal structural fillets sweep away sharp high-stress corner junctions.
* **Fastener Backout:** Thread-locking Loctite 242 secures all primary mechanical fastening locations.
* **Thread Stripping:** Brass inserts directly screwed into structural plastic (PLA).
* **Slide Jamming:** A 0.1mm physical spacing gap is maintained between sliding faces to protect against thermal expansion.
* **Floating Gates:** 10kOhm inline pull-down resistors ground the multiplexer signal lines when a roller breaks contact.
## Microcontroller Scalability Matrix
The board is designed for high drop-in compatibility across RP2040 AND ESP32C3 microcontrollers sharing a standard structural packaging footprint:
| Hardware Parameter | Seeed Studio XIAO ESP32C3 | Seeed Studio XIAO RP2040 |
|:---|:---|:---|
| **Processor Core** | Single-Core 32-bit RISC-V Architecture | Dual-Core 32-bit ARM Cortex-M0+ Core |
| **ADC Bit-Depth** | 12-bit Resolution ($0-4095$ bounds) | 12-bit Resolution ($0-4095$ bounds) |
| **Analog Noise Jitter** | Higher internal noise variance | Clean, lower baseline analog curves |
| **Firmware Overhead** | Demands aggressive digital software filtering | Operates on light data averaging loops |
| **Core Configuration** | Single I2C channel optimization | Configurable Programmable I/O blocks (PIO) |
### Pro-Repair & Circular Lifecycle
The tool utilizes standard M2 hardware fasteners throughout. Worn-down individual 3D-printed tines can be swapped out independently without disturbing the underlying sensor electronics or dual-PCB core architecture.
