Week 6 - Electronics Design

group page // repo source files // objectives


objectives >

hero shots >


Altium files:

chronology >

(In lieu of a quicklinks sidebar that mkdocs seems to provide by default)

Altium >

I use Altium at work, but I am also familiar with KiCad. I started out on Eagle when I began using ECAD tools, back in the day when they were still independently owned by CadSoft (honestly not that long ago).

attempt 1 - attiny44a >

oshpark >

I know others have done this, but I originally intended to benchmark oshpark turnaround vs cnc fabbing circuits.


I’ll fill in more details here later, but the short version is:

mods/fab - fabtinyisp >

I was on vacation for ~a week, and given how many bits I broke for the efab unit, I focused on making sure I could fab another fabtinyisp successfully.

mods montage


I succeeded, so I proceeded onto the actual board for this assignment.

efab - attiny >

efab efab

learned that I sent negative through mods, need to invert for mods to work properly. However, didn’t understand that at first. Assumed I had ignored design rules and made features too small. efab


should have done this during the efab week, but better late than never! feature benchmark to see if that was the cause of my bug. efab results are really good, so ruled that out. efab

fixed (inverted) artwork results. efab

the issue >

I thought I got components from Dan for the attiny44a, but we may have had a mixup… turns out I had all the parts for the samd11c. It took me a bit, but I implemented a new board using the libraries I built for the attiny for the samd11c.

attempt 2 - samd11c >

ecad >

another design montage! (I swear I’ll document this better later, it’s late and I need to function tomorrow).


some notes:

exporting gerbers. learned quite a few lessons during this process (described along with cam stuff below).


cam >

unfortunately didn’t capture the appropriate media here. a few lessons that I learned:

efab >


learned about another wonderful bug… seems like I should run at least one aircut before running any actual jobs with the mdx-20 (could just be a mods problem). some of the settings don’t “set” properly until after at least one run.

in this case, the origin is 10,10 by default, while I’ve been running jobs at 3,2. This explains the misalignment shown. efab

efab efab

unfortunately, I was doing this prior to work in the morning. Ran out of time, and learned that you should never rush when working with CNC… broke 2x 1/32” bits.

after I came back from work, did things properly and got a great result. efab efab

should’ve done some more homework before designing my usb footprint. pads line up fine, but definitely lacks the material required to align the usb in receptacle. efab

solder >

soldering mOnTaGe efab

snags I had to resolve:

ran out of 1uF caps and went searching for a switch part way through my solderwork, ended up reorganizing some of my inventory. efab

egads. turning a through hole switch into an SMT switch.

before: efab after: efab

hero shots >


Altium files:

concepts >

In EDA/ECAD design, components are described as symbols and footprints.

In Altium, symbols live in schematic libraries (schlib) and footprints live in pcb libraries (pcblib). It is typical to assign footprint(s) to a single symbol.

schdoc & schlib >

schdocs are where most altium projects start. the schematic describes the logical flow of your circuit design. It could be described as a flowchart.

component symbols are typically the most atomic units in the schematic. A typical flow starts with placing a mcu and related components, then adding in passive to configure the components. components are connected by wires, which represent different electrical nets.

a net describes pins and traces that are shorted together.

typically, I start by placing components from “global” (instead of “local”) schlib files that are available to any project. Different ecad tools call them different things, but I will stick with global and local.

pcbdoc & pcblib >

once your schematic is completed, you can update your pcbdoc with the netlist generated by the schdoc. Altium hides the netlist generation behind the scenes, to a degree.

design review >

usually, this is where a design review happens (probably prior to gerbers actually).

order/fab boards >

populate (or stuff) boards >

program >

test equipment >

gotchas >

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