Week 6 — Electronics design

Individual assignment — KiCad dev board

How I approached the week

I compared a few EDA options and stayed on KiCad because I want to own Gerbers and keep the project in Git without a paid seat. The long section below is intentionally instructional—ERC, net labels, and “update PCB from schematic” were the places I personally got stuck until I treated the schematic as logic only and the board as the only physical truth. If anything in your build differs (panel connector pinout, pull-up value), swap the numbers but keep the same discipline: verify pins against the datasheet before you order.

This section is written tutorial-style: each step states the goal, what to click or check in KiCad, and why it matters for a board that actually powers up. I used KiCad 7 (your minor version may differ; menus are similar in 8.x). If you replicate the circuit, verify pin numbers, voltage, and your display’s flex pinout against the datasheet—labels like WE/RE/CE here are placeholders for a memory-style interface and must match your panel.

How this board meets the assignment

Quick map from Fab “electronics design” expectations to what is on the sheet and the PCB:

Step 1 — Choose EDA and create a KiCad project

I compared three common options: KiCad (free, open-source, cross-platform), Eagle (Autodesk / Fusion ecosystem), and Altium Designer (commercial, common in industry). For Fab Academy style work—small runs, owning your own Gerbers, sharing projects on Git—KiCad is the most straightforward default.

Mental model (read this once; it saves hours later):

• The schematic is the logical design: symbols, nets, and rules (ERC). It is not the physical copper.
• Each symbol needs a matching footprint (physical land pattern) before manufacturing means anything.
• The PCB editor places those footprints and routes copper; DRC checks clearances and geometry against the fab process.
• Whenever you change the schematic, use Update PCB from Schematic so netlist and footprints stay in sync.

Actions in KiCad:

1. File → New Project… Create an empty folder; KiCad writes .kicad_pro (project), and you will add .kicad_sch (schematic) and .kicad_pcb (board).
2. Preferences → Manage Symbol Libraries… and Manage Footprint Libraries… Confirm the official KiCad libs are on, then add any XIAO / Fab tables your lab ships.
3. Open the Schematic Editor from the project manager. Save the sheet early (Ctrl+S / Cmd+S).

Step 2 — Draw the schematic (symbols, nets, power)

On the schematic I placed the XIAO RP2040 as the core (U1), a momentary switch with pull-up, an LED branch, and two connectors that expose the same display bus: an 8-pin FPC (J1) and a 2×8 header (J2). Net labels tie everything named the same net together without drawing long wires across the sheet.

Component-by-component (what to wire and why):

1. Power rails. Place global power symbols for +3V3 (or VCC_3V3 as labeled on your sheet) and GND. Connect them to every IC supply pin that needs them—in this case the XIAO’s 3V3 and GND pins. Every complete circuit needs a return path; “only drawing +3V3” without a deliberate GND net is the most common student ERC failure.
2. Pushbutton SW1 + pull-up R1 (example 1 kΩ on the screenshot). One side of the switch goes to GND; the other side goes to a net labeled L1 (here tied to MCU pin names such as P26_A0_D0 on the XIAO symbol). R1 pulls L1 toward 3V3 when the button is open, so the input is not floating. When you press the switch, L1 is shorted to GND → logic low (active-low style input). Swap the resistor to the value your lab standard uses (often 10 kΩ for lighter load); re-run ERC after any value change.
3. LED D1 + resistor R2 (220 Ω in the capture). GPIO drives L2 into the LED anode; cathode through R2 to GND. Physics check: at ~3.3 V forward drop, 220 Ω gives a few mA— plenty for indicator brightness without stressing a typical MCU pin (still confirm against your LED’s forward voltage and desired current).
4. FPC J1 (8-pin, 1.0 mm pitch symbol) and header J2. The sheet fans out control/data signals (WE, RE, CE, FPC_IO6–FPC_IO8), plus GND and display supply. Routing these on the MCU side must match how you bit-bang SPI/parallel/other modes in firmware and match the cable orientation (pin 1 on the flex, connector keying). If J1 and J2 are truly in parallel as drawn, treat them as “two ways to probe the same bus”—avoid driving conflicting sources into the same panel net.

Electrical Rules Check: in the schematic editor run Inspect → Electrical Rules Checker. Fix every error (floating inputs, mismatched pin types where KiCad warns) before syncing to PCB. Warnings are often informative for power pins and no-connects—read them; do not blanket dismiss.

Step 3 — Footprints and “Update PCB from Schematic”

For each symbol, assign a footprint that matches the part you will solder: passives as 0603/0805/etc., SW_Push to the exact switch from the drawer, J1 to the FPC’s vendor land pattern (or a verified KiCad footprint with the same pitch and stagger). Then:

1. Tools → Assign Footprints… Work left-to-right: filter library, pick footprint, apply. Missing footprints mean DRC cannot be trusted yet.
2. Open the PCB Editor. Run Tools → Update PCB from Schematic… Accept initial placement (everything may stack in a pile—that is normal).
3. Set File → Board Setup…: board thickness if known, minimum track/space compatible with Fab milling or your PCB vendor’s 6/6 or 8/8 mil class rules, via sizes, and netclass widths for power if you widen 3V3.

Step 4 — Placement: outline, connectors, bypass caps

Drag footprints out of the pile into a sane mechanical arrangement before you spend time routing:

• XIAO outline and USB egress: place the module so the USB edge lines up with the board edge you intend to expose; leave keepout for the connector shell.
• FPC along the edge that mates your flex cable’s bend radius; lock orientation so pin 1 on the footprint matches silkscreen pin 1.
• Switch at an edge you can reach with a finger on the assembled product.
• Decoupling capacitors (small ceramics on 3V3/ GND at the module) short and fat to the pins they serve—picture “as close as assembly allows,” not halfway across the board.

Step 5 — Route copper, pours, and run DRC

Route in an order that reduces pain: critical high-speed or bus signals and switch/reset-style lines first, then fill GND zones (copper pours) on relevant layers, then clean up escapes and vias.

• Keep the FPC breakout lanes organized—equal length is only needed when your interface doc says so; skew is often dominated by connector choice. Do avoid crossing broken ground under sensitive returns if your process is 2-layer.
• The switch net should not meander near noisy edges without a reason; short path to GND at the button reduces noise pickup.
• Re-run DRC until clearance and drill errors are resolved; silence “acceptable” exclusions with explicit reasons in your notes if you must waive something.

This layout is the direction I want for my final project carrier: RP2040 XIAO for software support, flat flex to the display, and a switch pattern I can reuse for configuration lines in firmware.

Revision 2 — connectors, Nanostat flashing, ESP32-S3

After I had already paid for and received the first PCB batch (on the order of CNY 100), laying the real board next to the rest of my system made a few mismatches obvious, so I went back into KiCad for a second spin rather than hacking the old outline with jumper wires everywhere.

In revision 2 I replaced the original display FPC with a smaller FPC footprint that matches the flex connector I actually want on the mechanical stack, and I added a 1×6 pin header right beside that area so those signals are easy to break out—useful for probing, dongles, or short harnesses during bring-up without only relying on the flex.

For the final project I plan to dock a Nanostat board that brings out six pads dedicated to flashing / field updates; among them, two pads are UART (serial) and must reach the main MCU. Earlier iterations were drawn around XIAO RP2040; this revision moves the design to Seeed XIAO ESP32-S3 so those two UART lines from the Nanostat interface can tie straight into the ESP32-S3 for download and serial logging, while the six-pad footprint still carries the wider programming pattern the Nanostat expects. The schematic screenshot at Figure 1 still reflects the RP2040 sheet I practiced on before the layout spin; mentally swap the MCU block for ESP32-S3 when you map GPIO names and USB/UART straps to this board revision.

Step 6 — Archive design files next to the site

Bundle the KiCad tree (.kicad_pro, .kicad_sch, .kicad_pcb, fp-lib-table / sym-lib-table if customized, and any project-local footprints) into a zip under something like design-files/week06/ so graders can open the exact project. Generated outputs deserve a tiny README or text file: board thickness, layer count, min trace/space, and ENIG vs HASL intent.

Figures on this page live under images/week06/…; open week06.html from the repo root or ship the whole static directory to your host.