Week 6: Electronics design

Individual assignment: KiCad dev board

How I approached the week

I compared a few EDA options and stayed on KiCad because I want to own Gerbers and keep the project in Git without a paid seat. The long section below is deliberately step-by-step. ERC, net labels, and “update PCB from schematic” were where I got stuck until I treated the schematic as logic only and the board as the only physical truth. If anything in your build differs (panel connector pinout, pull-up value), swap the numbers but keep the same discipline: verify pins against the datasheet before you order.

Each step states the goal, what to click in KiCad, and why it matters for a board that actually powers up. I used KiCad 7 (menus are similar in 8.x). If you replicate the circuit, verify pin numbers, voltage, and your display’s flex pinout against the datasheet. Labels like WE/RE/CE here are placeholders for a memory-style interface and must match your panel.

How this board meets the assignment

Quick map from Fab “electronics design” expectations to what is on the sheet and the PCB:

Step 1: Choose EDA and create a KiCad project

I compared three common options: KiCad (free, open-source, cross-platform), Eagle (Autodesk / Fusion ecosystem), and Altium Designer (commercial, common in industry). For Fab Academy style work (small runs, owning your own Gerbers, sharing projects on Git), KiCad is the most straightforward default.

Mental model (read this once; it saves hours later):

• The schematic is the logical design: symbols, nets, and rules (ERC). It is not the physical copper.
• Each symbol needs a matching footprint (physical land pattern) before manufacturing means anything.
• The PCB editor places those footprints and routes copper; DRC checks clearances and geometry against the fab process.
• Whenever you change the schematic, use Update PCB from Schematic so netlist and footprints stay in sync.

Actions in KiCad:

1. File → New Project… Create an empty folder; KiCad writes .kicad_pro (project), and you will add .kicad_sch (schematic) and .kicad_pcb (board).
2. Preferences → Manage Symbol Libraries… and Manage Footprint Libraries… Confirm the official KiCad libs are on, then add any XIAO / Fab tables your lab ships.
3. Open the Schematic Editor from the project manager. Save the sheet early (Ctrl+S / Cmd+S).

Step 2: Draw the schematic (symbols, nets, power)

The sheet centers on Seeed XIAO RP2040 (U1), a tactile switch with pull-up, an LED branch, and connectors toward the display bus (FPC J1 and 2×8 header J2). Below is the order I actually clicked through in the schematic editor; each screenshot matches one step.

2a. Place components

In the schematic editor, click the third icon in the right toolbar (Add symbol), search the library, and place parts on the sheet. The capture uses an LED as the example, but the same flow applies to the XIAO module, switch, resistors, and connectors.

2b. Place power symbols

Click the fourth icon in the right toolbar to add power symbols (GND, +3V3, and so on). Every supply pin needs a deliberate return path; I place both rails before I start wiring signal nets.

2c. Select the 3V3 symbol

From the power-symbol chooser, pick +3V3 (or the label your sheet uses, such as VCC_3V3). Place one instance near each block that needs logic supply; duplicate with C once the first copy is on the sheet.

2d. Connect 3V3

Wire each +3V3 symbol to the matching supply pins on U1 and to pull-ups (for example R1 on the switch net). Use the wire tool or click pin-to-pin; same net name ties distant nodes together when you add net labels later.

2e. Wire signals and mark unused pins

Finish the signal paths: switch + pull-up on L1, LED + series resistor on L2, display nets on J1/J2. For MCU or connector pins that stay unused, place a no-connect flag (the small X) so ERC does not treat them as floating inputs.

2f. Run ERC

Run Inspect → Electrical Rules Checker. Fix errors (missing GND, floating inputs, power pins not driven) before syncing to PCB. The capture below is the pass I kept before moving on to footprints.

Step 3: Footprints and “Update PCB from Schematic”

For each symbol, assign a footprint that matches the part you will solder: passives as 0603/0805/etc., SW_Push to the exact switch from the drawer, J1 to the FPC’s vendor land pattern (or a verified KiCad footprint with the same pitch and stagger). Then:

1. Tools → Assign Footprints… Work left-to-right: filter library, pick footprint, apply. Missing footprints mean DRC cannot be trusted yet.
2. Open the PCB Editor. Run Tools → Update PCB from Schematic… Accept initial placement (everything may stack in a pile; that is normal).
3. Set File → Board Setup…: board thickness if known, minimum track/space compatible with Fab milling or your PCB vendor’s 6/6 or 8/8 mil class rules, via sizes, and netclass widths for power if you widen 3V3.

Step 4: Placement: outline, connectors, bypass caps

Drag footprints out of the pile into a sane mechanical arrangement before you spend time routing:

• XIAO outline and USB egress: place the module so the USB edge lines up with the board edge you intend to expose; leave keepout for the connector shell.
• FPC along the edge that mates your flex cable’s bend radius; lock orientation so pin 1 on the footprint matches silkscreen pin 1.
• Switch at an edge you can reach with a finger on the assembled product.
• Decoupling capacitors (small ceramics on 3V3/ GND at the module) short and fat to the pins they serve. Picture “as close as assembly allows,” not halfway across the board.

Step 5: Route copper, pours, and run DRC

Route in an order that reduces pain: critical high-speed or bus signals and switch/reset-style lines first, then fill GND zones (copper pours) on relevant layers, then clean up escapes and vias.

• Keep the FPC breakout lanes organized. Equal length is only needed when your interface doc says so; skew is often dominated by connector choice. Do avoid crossing broken ground under sensitive returns if your process is 2-layer.
• The switch net should not meander near noisy edges without a reason; short path to GND at the button reduces noise pickup.
• Re-run DRC until clearance and drill errors are resolved; silence “acceptable” exclusions with explicit reasons in your notes if you must waive something.

This layout is the direction I want for my final project carrier: RP2040 XIAO for software support, flat flex to the display, and a switch pattern I can reuse for configuration lines in firmware.

Revision 2: connectors, Nanostat flashing, ESP32-S3

After I had already paid for and received the first PCB batch (on the order of CNY 100), laying the real board next to the rest of my system made a few mismatches obvious, so I went back into KiCad for a second spin rather than hacking the old outline with jumper wires everywhere.

In revision 2 I replaced the original display FPC with a smaller FPC footprint that matches the flex connector I actually want on the mechanical stack, and I added a 1×6 pin header right beside that area so those signals are easy to break out, useful for probing, dongles, or short harnesses during bring-up without only relying on the flex.

For the final project I plan to dock a Nanostat board that brings out six pads dedicated to flashing / field updates; among them, two pads are UART (serial) and must reach the main MCU. Earlier iterations were drawn around XIAO RP2040; this revision moves the design to Seeed XIAO ESP32-S3 so those two UART lines from the Nanostat interface can tie straight into the ESP32-S3 for download and serial logging, while the six-pad footprint still carries the wider programming pattern the Nanostat expects. The schematic steps in Step 2 still reflect the RP2040 sheet I practiced on before the layout spin; mentally swap the MCU block for ESP32-S3 when you map GPIO names and USB/UART straps to this board revision.

Design files (download)

KiCad sources for this week’s board (revision 1, XIAO RP2040 carrier). Open both in KiCad 7/8: schematic first, then the matching PCB. If the browser shows plain text instead of saving, use Save As… or right-click → Download linked file so the extension stays .kicad_sch / .kicad_pcb.

• Schematic — v1.kicad_sch
• PCB layout — v1.kicad_pcb

Figures on this page live under images/week06/…; design sources under design-files/week06/….