5. Embedded programming¶
This week I worked on defining my final project idea and started to getting used to the documentation process.
Studying topics¶
Von Neumann Vs Harvard Architecture¶
The image compares the Von Neumann and Harvard architectures, two fundamental computing architectures. The Von Neumann architecture (left) uses a single memory unit for both data and instructions, with a shared data and address bus, leading to a bottleneck where the CPU must fetch instructions and data sequentially, slowing down performance. This design is widely used in general-purpose computers due to its simplicity and flexibility. In contrast, the Harvard architecture (right) separates program memory and data memory, each with its own dedicated buses, allowing simultaneous fetching of instructions and data, significantly improving processing speed and efficiency. This makes it ideal for embedded systems, DSPs, and microcontrollers, where high-speed execution is crucial. Modern processors often use a modified Harvard architecture, combining elements of both to optimize performance. For more details, refer to the source article on Medium:
RISC-and-CISC¶
This image illustrates the difference between RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) architectures by depicting their structural design. The RISC architecture (left) features a hardwired control unit, which directly interacts with the instruction cache and command memory, enabling faster execution of simple instructions. It emphasizes a simplified instruction set with uniform execution cycles, leading to higher efficiency and better performance in modern processors. In contrast, the CISC architecture (right) employs a control unit (CU) with control memory, which interacts with the data path, cache, and main memory. This structure supports complex multi-step instructions, reducing the number of instructions in a program but requiring longer execution times per instruction. While RISC prioritizes speed and efficiency with a streamlined approach, CISC focuses on reducing program complexity at the cost of slower execution cycles. Modern processors often adopt a hybrid approach, integrating elements of both architectures to balance performance and complexity.
For more details, refer to the source article on geeksforgeeks:
Microprocessor-vs-Microcontroller¶
These images compare a Microprocessor and a Microcontroller, highlighting their structural and functional differences. A microprocessor (left) consists of an Arithmetic Logic Unit (ALU), Control Unit, and Register Array, but it requires external components like RAM, ROM, and I/O devices to function. It is designed for general-purpose computing, making it ideal for high-performance tasks like running operating systems in computers (e.g., Intel Core i7). In contrast, a microcontroller (right) is a self-contained system that integrates the CPU, RAM, ROM, I/O ports, timers, and serial communication within a single chip (e.g., Microchip ATmega328P). This makes microcontrollers more power-efficient and suitable for embedded systems, automation, and real-time applications such as IoT devices, robotics, and home appliances. While microprocessors focus on processing power and flexibility, microcontrollers prioritize compact, low-power, and task-specific operations.
CPU GPU¶
It compares the architectures of a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit), highlighting their structural differences. The CPU (left) consists of a control unit, a few Arithmetic Logic Units (ALUs), cache memory, and DRAM. CPUs are optimized for sequential processing, handling complex tasks with fewer but more powerful cores, making them ideal for general-purpose computing, operating systems, and single-threaded applications. On the other hand, the GPU (right) features many smaller ALUs arranged in parallel, allowing it to handle massive parallel processing tasks. GPUs excel at graphics rendering, scientific computing, AI processing, and deep learning by efficiently managing thousands of simultaneous operations. While CPUs focus on low-latency, high-precision computing, GPUs prioritize high-throughput parallelism, making them essential for modern gaming, machine learning, and computational workloads.
Embedded FPGA¶
This image illustrates the architecture of an Embedded FPGA (Field-Programmable Gate Array) within a System-on-Chip (SoC) with Programmable Acceleration. The design integrates multiple CPU clusters, each with its own L2 cache, allowing efficient multi-core processing. The Embedded FPGA provides programmable hardware acceleration, enabling high-performance computing for specialized tasks such as AI, signal processing, and real-time data processing. A cache-coherent interconnect ensures seamless communication between the CPU clusters and the FPGA, optimizing data transfer and computational efficiency. The architecture also includes essential components such as a security bridge for secure data access, a DDR controller for memory management, and interfaces for PCIe and Ethernet connectivity, ensuring high-speed data communication. This hybrid SoC architecture balances general-purpose computing with flexible hardware acceleration, making it ideal for applications requiring high efficiency, adaptability, and low latency processing.
For more details, refer to the source article on icdrex.com:
Register Memory¶
It represents the hierarchical structure of memory in a computer system, focusing on register memory, main memory, and storage devices. The CPU contains essential components such as registers, the Arithmetic & Logic Unit (ALU), and the Control Unit, which work together to process instructions. Registers are the fastest memory units, directly integrated into the CPU, storing temporary data for quick access and reducing latency during execution. The main memory (RAM) interacts with the CPU to store active programs and data that require quick access, but it is volatile and loses data when power is off. The I/O controller manages communication between the CPU and external storage devices, such as disk drives, which provide long-term data storage. This architecture highlights the role of registers as the fastest memory, followed by RAM for temporary data storage, and disk drives for persistent storage, ensuring efficient data processing and retrieval.
For more details, refer to the source article on geeksforgeeks.org:
Ports¶
Practical learning¶
Worwi Simulation¶
// WOKWI- ESP32 simulator- Blinking LED - sketch.ino () {
//
sketch.ino
int LED1=26;
void setup() {
// put your setup code here, to run once:
Serial.begin(115200);
Serial.println("Hello, ESP32!");
pinMode(LED1, OUTPUT);
}
void loop() {
digitalWrite(LED1, HIGH);
Serial.println('ON');
delay(1000);
digitalWrite(LED1, LOW);
Serial.println('OFF');
delay(1000);
// put your main code here, to run repeatedly:
// this speeds up the simulation
}
diagram.json
{
"version": 1,
"author": "Erik A",
"editor": "wokwi",
"parts": [
{ "type": "board-esp32-devkit-c-v4", "id": "esp", "top": 0, "left": 0, "attrs": {} },
{
"type": "wokwi-led",
"id": "led1",
"top": 34.8,
"left": -101.8,
"attrs": { "color": "green" }
}
],
"connections": [
[ "esp:TX", "$serialMonitor:RX", "", [] ],
[ "esp:RX", "$serialMonitor:TX", "", [] ],
[ "led1:A", "esp:26", "green", [ "v38.4", "h76.8" ] ],
[ "led1:C", "esp:GND.1", "green", [ "v76.8", "h86.8" ] ]
],
"dependencies": {}
00:26.947101%
INPull-up
INPull-down
INPull-down
INPull-up
MTDI
MTCK
MTMS
MTDO
INFloating
INFloating
INFloating
INFloating
INFloating
INFloating
INFloating
INFloating
OUTHigh
INFloating
INFloating
INFloating
INFloating
INFloating
INFloating
INFloating
SPI1HD
SPI1WP
SPI1CS0
UART0TX
UART0RX
SPI1MOSI
SPI1MISO
SPI1CLK
ets Jul 29 2019 12:21:46
rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT)
configsip: 0, SPIWP:0xee
clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00
mode:DIO, clock div:2
load:0x3fff0030,len:1156
load:0x40078000,len:11456
ho 0 tail 12 room 4
load:0x40080400,len:2972
entry 0x400805dc
Hello, ESP32!
20302
5195334
}
