21:33:42.864 -> ets Jun 8 2016 00:22:57 21:33:42.864 -> 21:33:42.864 -> rst:0x1 (POWERON_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:42.864 -> configsip: 0, SPIWP:0xee 21:33:42.864 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:42.897 -> mode:DIO, clock div:1 21:33:42.897 -> load:0x3fff0018,len:4 21:33:42.897 -> load:0x3fff001c,len:1216 21:33:42.897 -> ho 0 tail 12 room 4 21:33:42.897 -> load:0x40078000,len:10944 21:33:42.897 -> load:0x40080400,len:6388 21:33:42.897 -> entry 0x400806b4 21:33:42.897 -> ets Jun 8 2016 00:22:57 21:33:42.897 -> 21:33:42.897 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:42.897 -> configsip: 0, SPIWP:0xee 21:33:42.897 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:42.931 -> mode:DIO, clock div:1 21:33:42.931 -> load:0x3fff0018,len:4 21:33:42.931 -> load:0x3fff001c,len:1216 21:33:42.931 -> ho 0 tail 12 room 4 21:33:42.931 -> load:0x40078000,len:10944 21:33:42.931 -> load:0x00080000,len:4340 21:33:43.239 -> ets Jun 8 2016 00:22:57 21:33:43.239 -> 21:33:43.239 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:43.239 -> configsip: 0, SPIWP:0xee 21:33:43.239 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:43.239 -> mode:DIO, clock div:1 21:33:43.239 -> load:0x3fff0018,len:4 21:33:43.239 -> load:0x3fff001c,len:1216 21:33:43.239 -> ho 0 tail 12 room 4 21:33:43.239 -> load:0x40078000,len:10944 21:33:43.239 -> load:0x00080000,len:4340 21:33:43.557 -> ets Jun 8 2016 00:22:57 21:33:43.557 -> 21:33:43.557 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:43.557 -> configsip: 0, SPIWP:0xee 21:33:43.557 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:43.557 -> mode:DIO, clock div:1 21:33:43.557 -> load:0x3fff0018,len:4 21:33:43.557 -> load:0x3fff001c,len:1216 21:33:43.557 -> ho 0 tail 12 room 4 21:33:43.557 -> load:0x40078000,len:10944 21:33:43.591 -> load:0x00080000,len:4340 21:33:43.862 -> ets Jun 8 2016 00:22:57 21:33:43.862 -> 21:33:43.862 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:43.897 -> configsip: 0, SPIWP:0xee 21:33:43.897 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:43.897 -> mode:DIO, clock div:1 21:33:43.897 -> load:0x3fff0018,len:4 21:33:43.897 -> load:0x3fff001c,len:1216 21:33:43.897 -> ho 0 tail 12 room 4 21:33:43.897 -> load:0x40078000,len:10944 21:33:43.897 -> load:0x00080000,len:4340 21:33:44.203 -> ets Jun 8 2016 00:22:57 21:33:44.203 -> 21:33:44.203 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:44.203 -> configsip: 0, SPIWP:0xee 21:33:44.203 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:44.203 -> mode:DIO, clock div:1 21:33:44.203 -> load:0x3fff0018,len:4 21:33:44.203 -> load:0x3fff001c,len:1216 21:33:44.237 -> ho 0 tail 12 room 4 21:33:44.237 -> load:0x40078000,len:10944 21:33:44.237 -> load:0x00080000,len:4340 21:33:44.515 -> ets Jun 8 2016 00:22:57 21:33:44.515 -> 21:33:44.515 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:44.515 -> configsip: 0, SPIWP:0xee 21:33:44.549 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:44.549 -> mode:DIO, clock div:1 21:33:44.549 -> load:0x3fff0018,len:4 21:33:44.549 -> load:0x3fff001c,len:1216 21:33:44.549 -> ho 0 tail 12 room 4 21:33:44.549 -> load:0x40078000,len:10944 21:33:44.549 -> load:0x00080000,len:4340 21:33:44.855 -> ets Jun 8 2016 00:22:57 21:33:44.855 -> 21:33:44.855 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:44.855 -> configsip: 0, SPIWP:0xee 21:33:44.855 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:44.855 -> mode:DIO, clock div:1 21:33:44.855 -> load:0x3fff0018,len:4 21:33:44.855 -> load:0x3fff001c,len:1216 21:33:44.855 -> ho 0 tail 12 room 4 21:33:44.890 -> load:0x40078000,len:10944 21:33:44.890 -> load:0x00080000,len:4340 21:33:45.157 -> ets Jun 8 2016 00:22:57 21:33:45.191 -> 21:33:45.191 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:45.191 -> configsip: 0, SPIWP:0xee 21:33:45.191 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:45.191 -> mode:DIO, clock div:1 21:33:45.191 -> load:0x3fff0018,len:4 21:33:45.191 -> load:0x3fff001c,len:1216 21:33:45.191 -> ho 0 tail 12 room 4 21:33:45.191 -> load:0x40078000,len:10944 21:33:45.191 -> load:0x00080000,len:4340 21:33:45.496 -> ets Jun 8 2016 00:22:57 21:33:45.496 -> 21:33:45.496 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:45.496 -> configsip: 0, SPIWP:0xee 21:33:45.496 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:45.529 -> mode:DIO, clock div:1 21:33:45.529 -> load:0x3fff0018,len:4 21:33:45.529 -> load:0x3fff001c,len:1216 21:33:45.529 -> ho 0 tail 12 room 4 21:33:45.529 -> load:0x40078000,len:10944 21:33:45.529 -> load:0x00080000,len:4340 21:33:45.808 -> ets Jun 8 2016 00:22:57 21:33:45.846 -> 21:33:45.846 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:45.846 -> configsip: 0, SPIWP:0xee 21:33:45.846 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:45.846 -> mode:DIO, clock div:1 21:33:45.846 -> load:0x3fff0018,len:4 21:33:45.846 -> load:0x3fff001c,len:1216 21:33:45.846 -> ho 0 tail 12 room 4 21:33:45.846 -> load:0x40078000,len:10944 21:33:45.846 -> load:0x00080000,len:4340 21:33:46.172 -> ets Jun 8 2016 00:22:57 21:33:46.172 -> 21:33:46.172 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:46.172 -> configsip: 0, SPIWP:0xee 21:33:46.172 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:46.172 -> mode:DIO, clock div:1 21:33:46.172 -> load:0x3fff0018,len:4 21:33:46.172 -> load:0x3fff001c,len:1216 21:33:46.172 -> ho 0 tail 12 room 4 21:33:46.172 -> load:0x40078000,len:10944 21:33:46.172 -> load:0x00080000,len:4340 21:33:46.462 -> ets Jun 8 2016 00:22:57 21:33:46.462 -> 21:33:46.462 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:46.500 -> configsip: 0, SPIWP:0xee 21:33:46.500 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:46.500 -> mode:DIO, clock div:1 21:33:46.500 -> load:0x3fff0018,len:4 21:33:46.500 -> load:0x3fff001c,len:1216 21:33:46.500 -> ho 0 tail 12 room 4 21:33:46.500 -> load:0x40078000,len:10944 21:33:46.500 -> load:0x00080000,len:4340 21:33:46.789 -> ets Jun 8 2016 00:22:57 21:33:46.789 -> 21:33:46.789 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:46.789 -> configsip: 0, SPIWP:0xee 21:33:46.824 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:46.824 -> mode:DIO, clock div:1 21:33:46.824 -> load:0x3fff0018,len:4 21:33:46.824 -> load:0x3fff001c,len:1216 21:33:46.824 -> ho 0 tail 12 room 4 21:33:46.824 -> load:0x40078000,len:10944 21:33:46.824 -> load:0x00080000,len:4340 21:33:47.131 -> ets Jun 8 2016 00:22:57 21:33:47.131 -> 21:33:47.131 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:47.131 -> configsip: 0, SPIWP:0xee 21:33:47.131 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:47.131 -> mode:DIO, clock div:1 21:33:47.131 -> load:0x3fff0018,len:4 21:33:47.131 -> load:0x3fff001c,len:1216 21:33:47.131 -> ho 0 tail 12 room 4 21:33:47.168 -> load:0x40078000,len:10944 21:33:47.168 -> load:0x00080000,len:4340 21:33:47.451 -> ets Jun 8 2016 00:22:57 21:33:47.451 -> 21:33:47.451 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:47.451 -> configsip: 0, SPIWP:0xee 21:33:47.451 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:47.451 -> mode:DIO, clock div:1 21:33:47.451 -> load:0x3fff0018,len:4 21:33:47.484 -> load:0x3fff001c,len:1216 21:33:47.484 -> ho 0 tail 12 room 4 21:33:47.484 -> load:0x40078000,len:10944 21:33:47.484 -> load:0x00080000,len:4340 21:33:47.764 -> ets Jun 8 2016 00:22:57 21:33:47.764 -> 21:33:47.764 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:47.801 -> configsip: 0, SPIWP:0xee 21:33:47.801 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:47.801 -> mode:DIO, clock div:1 21:33:47.801 -> load:0x3fff0018,len:4 21:33:47.801 -> load:0x3fff001c,len:1216 21:33:47.801 -> ho 0 tail 12 room 4 21:33:47.801 -> load:0x40078000,len:10944 21:33:47.801 -> load:0x00080000,len:4340 21:33:48.106 -> ets Jun 8 2016 00:22:57 21:33:48.106 -> 21:33:48.106 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:48.106 -> configsip: 0, SPIWP:0xee 21:33:48.106 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:48.106 -> mode:DIO, clock div:1 21:33:48.106 -> load:0x3fff0018,len:4 21:33:48.106 -> load:0x3fff001c,len:1216 21:33:48.106 -> ho 0 tail 12 room 4 21:33:48.141 -> load:0x40078000,len:10944 21:33:48.141 -> load:0x00080000,len:4340 21:33:48.414 -> ets Jun 8 2016 00:22:57 21:33:48.414 -> 21:33:48.414 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:48.452 -> configsip: 0, SPIWP:0xee 21:33:48.452 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:48.452 -> mode:DIO, clock div:1 21:33:48.452 -> load:0x3fff0018,len:4 21:33:48.452 -> load:0x3fff001c,len:1216 21:33:48.452 -> ho 0 tail 12 room 4 21:33:48.452 -> load:0x40078000,len:10944 21:33:48.452 -> load:0x00080000,len:4340 21:33:48.763 -> ets Jun 8 2016 00:22:57 21:33:48.763 -> 21:33:48.763 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:48.763 -> configsip: 0, SPIWP:0xee 21:33:48.763 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:48.763 -> mode:DIO, clock div:1 21:33:48.763 -> load:0x3fff0018,len:4 21:33:48.763 -> load:0x3fff001c,len:1216 21:33:48.763 -> ho 0 tail 12 room 4 21:33:48.763 -> load:0x40078000,len:10944 21:33:48.763 -> load:0x00080000,len:4340 21:33:49.067 -> ets Jun 8 2016 00:22:57 21:33:49.067 -> 21:33:49.067 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:49.067 -> configsip: 0, SPIWP:0xee 21:33:49.102 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:49.102 -> mode:DIO, clock div:1 21:33:49.102 -> load:0x3fff0018,len:4 21:33:49.102 -> load:0x3fff001c,len:1216 21:33:49.102 -> ho 0 tail 12 room 4 21:33:49.102 -> load:0x40078000,len:10944 21:33:49.102 -> load:0x00080000,len:4340 21:33:49.423 -> ets Jun 8 2016 00:22:57 21:33:49.423 -> 21:33:49.423 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:49.423 -> configsip: 0, SPIWP:0xee 21:33:49.423 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:49.423 -> mode:DIO, clock div:1 21:33:49.423 -> load:0x3fff0018,len:4 21:33:49.423 -> load:0x3fff001c,len:1216 21:33:49.423 -> ho 0 tail 12 room 4 21:33:49.423 -> load:0x40078000,len:10944 21:33:49.423 -> load:0x00080000,len:4340 21:33:49.725 -> ets Jun 8 2016 00:22:57 21:33:49.725 -> 21:33:49.725 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:49.725 -> configsip: 0, SPIWP:0xee 21:33:49.725 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:49.725 -> mode:DIO, clock div:1 21:33:49.762 -> load:0x3fff0018,len:4 21:33:49.762 -> load:0x3fff001c,len:1216 21:33:49.762 -> ho 0 tail 12 room 4 21:33:49.762 -> load:0x40078000,len:10944 21:33:49.762 -> load:0x00080000,len:4340 21:33:50.033 -> ets Jun 8 2016 00:22:57 21:33:50.067 -> 21:33:50.067 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:50.067 -> configsip: 0, SPIWP:0xee 21:33:50.067 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:50.067 -> mode:DIO, clock div:1 21:33:50.067 -> load:0x3fff0018,len:4 21:33:50.067 -> load:0x3fff001c,len:1216 21:33:50.067 -> ho 0 tail 12 room 4 21:33:50.067 -> load:0x40078000,len:10944 21:33:50.067 -> load:0x00080000,len:4340 21:33:50.376 -> ets Jun 8 2016 00:22:57 21:33:50.376 -> 21:33:50.376 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:50.376 -> configsip: 0, SPIWP:0xee 21:33:50.376 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:50.376 -> mode:DIO, clock div:1 21:33:50.376 -> load:0x3fff0018,len:4 21:33:50.414 -> load:0x3fff001c,len:1216 21:33:50.414 -> ho 0 tail 12 room 4 21:33:50.414 -> load:0x40078000,len:10944 21:33:50.414 -> load:0x00080000,len:4340 21:33:50.696 -> ets Jun 8 2016 00:22:57 21:33:50.696 -> 21:33:50.696 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:50.696 -> configsip: 0, SPIWP:0xee 21:33:50.696 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:50.731 -> mode:DIO, clock div:1 21:33:50.731 -> load:0x3fff0018,len:4 21:33:50.731 -> load:0x3fff001c,len:192 21:33:50.731 -> ho 0 tail 12 room 4 21:33:50.731 -> load:0x725f4074,len:879902836 21:33:50.731 -> 1162 mmu set 00010000, pos 00010000 21:33:50.731 -> 1162 mmu set 00020000, pos 00020000 21:33:50.731 -> 1162 mmu set 00030000, pos 00030000 21:33:50.767 -> 1162 mmu set 00040000, pos 00040000 21:33:50.767 -> 1162 mmu set 00050000, pos 00050000 21:33:50.767 -> 1162 mmu set 00060000, pos 00060000 21:33:50.767 -> 1162 mmu set 00070000, pos 00070000 21:33:50.803 -> 1162 mmu set 00080000, pos 00080000 21:33:50.803 -> 1162 mmu set 00090000, pos 00090000 21:33:50.803 -> 1162 mmu set 000a0000, pos 000a0000 21:33:50.841 -> 1162 mmu set 000b0000, pos 000b0000 21:33:50.841 -> 1162 mmu set 000c0000, pos 000c0000 21:33:50.841 -> 1162 mmu set 000d0000, pos 000d0000 21:33:50.841 -> 1162 mmu set 000e0000, pos 000e0000 21:33:50.875 -> 1162 mmu set 000f0000, pos 000f0000 21:33:50.875 -> 1162 mmu set 00100000, pos 00100000 21:33:50.875 -> 1162 mmu set 00110000, pos 00110000 21:33:50.875 -> 1162 mmu set 00120000, pos 00120000 21:33:50.913 -> 1162 mmu set 00130000, pos 00130000 21:33:50.913 -> 1162 mmu set 00140000, pos 00140000 21:33:50.913 -> 1162 mmu set 00150000, pos 00150000 21:33:50.913 -> 1162 mmu set 00160000, pos 00160000 21:33:50.947 -> 1162 mmu set 00170000, pos 00170000 21:33:50.947 -> 1162 mmu set 00180000, pos 00180000 21:33:50.947 -> 1162 mmu set 00190000, pos 00190000 21:33:50.985 -> 1162 mmu set 001a0000, pos 001a0000 21:33:50.985 -> 1162 mmu set 001b0000, pos 001b0000 21:33:50.985 -> 1162 mmu set 001c0000, pos 001c0000 21:33:50.985 -> 1162 mmu set 001d0000, pos 001d0000 21:33:51.018 -> 1162 mmu set 001e0000, pos 001e0000 21:33:51.018 -> 1162 mmu set 001f0000, pos 001f0000 21:33:51.018 -> ets Jun 8 2016 00:22:57 21:33:51.018 -> 21:33:51.018 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:51.018 -> configsip: 0, SPIWP:0xee 21:33:51.051 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:51.051 -> mode:DIO, clock div:1 21:33:51.051 -> load:0x3fff0018,len:4 21:33:51.051 -> load:0x3fff001c,len:1216 21:33:51.051 -> ho 0 tail 12 room 4 21:33:51.051 -> load:0x40078000,len:10944 21:33:51.051 -> load:0x00080000,len:4340 21:33:51.184 -> ets Jun 8 2016 00:22:57 21:33:51.184 -> 21:33:51.184 -> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:51.184 -> configsip: 0, SPIWP:0xee 21:33:51.184 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:51.184 -> mode:DIO, clock div:1 21:33:51.184 -> load:0x3fff0018,len:4 21:33:51.184 -> load:0x3fff001c,len:1216 21:33:51.219 -> ho 0 tail 12 room 4 21:33:51.219 -> load:0x40078000,len:10944 21:33:51.219 -> load:0x40080400,len:6388 21:33:51.219 -> entry 0x400806b4 21:33:51.219 -> ets Jun 8 2016 00:22:57 21:33:51.219 -> 21:33:51.219 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:51.219 -> configsip: 0, SPIWP:0xee 21:33:51.219 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:51.219 -> mode:DIO, clock div:1 21:33:51.219 -> load:0x3fff0018,len:4 21:33:51.219 -> load:0x3fff001c,len:1216 21:33:51.219 -> ho 0 tail 12 room 4 21:33:51.219 -> load:0x40078000,len:10944 21:33:51.253 -> load:0x00080000,len:4340 21:33:51.527 -> ets Jun 8 2016 00:22:57 21:33:51.527 -> 21:33:51.527 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:51.565 -> configsip: 0, SPIWP:0xee 21:33:51.565 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:51.565 -> mode:DIO, clock div:1 21:33:51.565 -> load:0x3fff0018,len:4 21:33:51.565 -> load:0x3fff001c,len:1216 21:33:51.565 -> ho 0 tail 12 room 4 21:33:51.565 -> load:0x40078000,len:10944 21:33:51.565 -> load:0x00080000,len:4340 21:33:51.870 -> ets Jun 8 2016 00:22:57 21:33:51.870 -> 21:33:51.870 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:51.870 -> configsip: 0, SPIWP:0xee 21:33:51.870 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:51.870 -> mode:DIO, clock div:1 21:33:51.870 -> load:0x3fff0018,len:4 21:33:51.870 -> load:0x3fff001c,len:1216 21:33:51.870 -> ho 0 tail 12 room 4 21:33:51.870 -> load:0x40078000,len:10944 21:33:51.906 -> load:0x00080000,len:4340 21:33:52.182 -> ets Jun 8 2016 00:22:57 21:33:52.182 -> 21:33:52.182 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:52.182 -> configsip: 0, SPIWP:0xee 21:33:52.182 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:52.218 -> mode:DIO, clock div:1 21:33:52.218 -> load:0x3fff0018,len:4 21:33:52.218 -> load:0x3fff001c,len:1216 21:33:52.218 -> ho 0 tail 12 room 4 21:33:52.218 -> load:0x40078000,len:10944 21:33:52.218 -> load:0x00080000,len:4340 21:33:52.523 -> ets Jun 8 2016 00:22:57 21:33:52.523 -> 21:33:52.523 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:52.523 -> configsip: 0, SPIWP:0xee 21:33:52.523 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:52.523 -> mode:DIO, clock div:1 21:33:52.523 -> load:0x3fff0018,len:4 21:33:52.523 -> load:0x3fff001c,len:1216 21:33:52.523 -> ho 0 tail 12 room 4 21:33:52.523 -> load:0x40078000,len:10944 21:33:52.523 -> load:0x00080000,len:4340 21:33:52.833 -> ets Jun 8 2016 00:22:57 21:33:52.833 -> 21:33:52.833 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:52.833 -> configsip: 0, SPIWP:0xee 21:33:52.833 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:52.867 -> mode:DIO, clock div:1 21:33:52.867 -> load:0x3fff0018,len:4 21:33:52.867 -> load:0x3fff001c,len:1216 21:33:52.867 -> ho 0 tail 12 room 4 21:33:52.867 -> load:0x40078000,len:10944 21:33:52.867 -> load:0x00080000,len:4340 21:33:53.175 -> ets Jun 8 2016 00:22:57 21:33:53.175 -> 21:33:53.175 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:53.175 -> configsip: 0, SPIWP:0xee 21:33:53.175 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:53.175 -> mode:DIO, clock div:1 21:33:53.175 -> load:0x3fff0018,len:4 21:33:53.175 -> load:0x3fff001c,len:1216 21:33:53.175 -> ho 0 tail 12 room 4 21:33:53.175 -> load:0x40078000,len:10944 21:33:53.175 -> load:0x00080000,len:4340 21:33:53.529 -> ets Jun 8 2016 00:22:57 21:33:53.529 -> 21:33:53.529 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:53.529 -> configsip: 0, SPIWP:0xee 21:33:53.529 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:53.529 -> mode:DIO, clock div:1 21:33:53.529 -> load:0x3fff0018,len:4 21:33:53.529 -> load:0x3fff001c,len:1216 21:33:53.529 -> ho 0 tail 12 room 4 21:33:53.529 -> load:0x40078000,len:10944 21:33:53.529 -> load:0x00080000,len:4340 21:33:53.802 -> ets Jun 8 2016 00:22:57 21:33:53.802 -> 21:33:53.802 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:53.836 -> configsip: 0, SPIWP:0xee 21:33:53.836 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:53.836 -> mode:DIO, clock div:1 21:33:53.836 -> load:0x3fff0018,len:4 21:33:53.836 -> load:0x3fff001c,len:192 21:33:53.836 -> ho 0 tail 12 room 4 21:33:53.836 -> load:0x725f4174,len:879902836 21:33:53.836 -> 1162 mmu set 00010000, pos 00010000 21:33:53.836 -> 1162 mmu set 00020000, pos 00020000 21:33:53.871 -> 1162 mmu set 00030000, pos 00030000 21:33:53.871 -> 1162 mmu set 00040000, pos 00040000 21:33:53.871 -> 1162 mmu set 00050000, pos 00050000 21:33:53.871 -> 1162 mmu set 00060000, pos 00060000 21:33:53.907 -> 1162 mmu set 00070000, pos 00070000 21:33:53.907 -> 1162 mmu set 00080000, pos 00080000 21:33:53.907 -> 1162 mmu set 00090000, pos 00090000 21:33:53.943 -> 1162 mmu set 000a0000, pos 000a0000 21:33:53.943 -> 1162 mmu set 000b0000, pos 000b0000 21:33:53.943 -> 1162 mmu set 000c0000, pos 000c0000 21:33:53.943 -> 1162 mmu set 000d0000, pos 000d0000 21:33:53.980 -> 1162 mmu set 000e0000, pos 000e0000 21:33:53.980 -> 1162 mmu set 000f0000, pos 000f0000 21:33:53.980 -> 1162 mmu set 00100000, pos 00100000 21:33:53.980 -> 1162 mmu set 00110000, pos 00110000 21:33:54.014 -> 1162 mmu set 00120000, pos 00120000 21:33:54.014 -> 1162 mmu set 00130000, pos 00130000 21:33:54.014 -> 1162 mmu set 00140000, pos 00140000 21:33:54.014 -> 1162 mmu set 00150000, pos 00150000 21:33:54.048 -> 1162 mmu set 00160000, pos 00160000 21:33:54.048 -> 1162 mmu set 00170000, pos 00170000 21:33:54.048 -> 1162 mmu set 00180000, pos 00180000 21:33:54.094 -> 1162 mmu set 00190000, pos 00190000 21:33:54.094 -> 1162 mmu set 001a0000, pos 001a0000 21:33:54.094 -> 1162 mmu set 001b0000, pos 001b0000 21:33:54.094 -> 1162 mmu set 001c0000, pos 001c0000 21:33:54.121 -> 1162 mmu set 001d0000, pos 001d0000 21:33:54.121 -> 1162 mmu set 001e0000, pos 001e0000 21:33:54.121 -> 1162 mmu set 001f0000, pos 001f0000 21:33:54.157 -> ets Jun 8 2016 00:22:57 21:33:54.157 -> 21:33:54.157 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:54.157 -> configsip: 0, SPIWP:0xee 21:33:54.157 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:54.157 -> mode:DIO, clock div:1 21:33:54.157 -> load:0x3fff0018,len:4 21:33:54.157 -> load:0x3fff001c,len:1216 21:33:54.157 -> ho 0 tail 12 room 4 21:33:54.157 -> load:0x40078000,len:10944 21:33:54.157 -> load:0x00080000,len:4340 21:33:54.464 -> ets Jun 8 2016 00:22:57 21:33:54.464 -> 21:33:54.464 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:54.464 -> configsip: 0, SPIWP:0xee 21:33:54.464 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:54.464 -> mode:DIO, clock div:1 21:33:54.464 -> load:0x3fff0018,len:4 21:33:54.499 -> load:0x3fff001c,len:1216 21:33:54.499 -> ho 0 tail 12 room 4 21:33:54.499 -> load:0x40078000,len:10944 21:33:54.499 -> load:0x00080000,len:4340 21:33:54.779 -> ets Jun 8 2016 00:22:57 21:33:54.779 -> 21:33:54.779 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:54.779 -> configsip: 0, SPIWP:0xee 21:33:54.816 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:54.816 -> mode:DIO, clock div:1 21:33:54.816 -> load:0x3fff0018,len:4 21:33:54.816 -> load:0x3fff001c,len:192 21:33:54.816 -> ho 0 tail 12 room 4 21:33:54.816 -> load:0x725f4074,len:879902836 21:33:54.816 -> 1162 mmu set 00010000, pos 00010000 21:33:54.816 -> 1162 mmu set 00020000, pos 00020000 21:33:54.816 -> 1162 mmu set 00030000, pos 00030000 21:33:54.852 -> 1162 mmu set 00040000, pos 00040000 21:33:54.852 -> 1162 mmu set 00050000, pos 00050000 21:33:54.852 -> 1162 mmu set 00060000, pos 00060000 21:33:54.888 -> 1162 mmu set 00070000, pos 00070000 21:33:54.888 -> 1162 mmu set 00080000, pos 00080000 21:33:54.888 -> 1162 mmu set 00090000, pos 00090000 21:33:54.888 -> 1162 mmu set 000a0000, pos 000a0000 21:33:54.922 -> 1162 mmu set 000b0000, pos 000b0000 21:33:54.922 -> 1162 mmu set 000c0000, pos 000c0000 21:33:54.922 -> 1162 mmu set 000d0000, pos 000d0000 21:33:54.922 -> 1162 mmu set 000e0000, pos 000e0000 21:33:54.955 -> 1162 mmu set 000f0000, pos 000f0000 21:33:54.955 -> 1162 mmu set 00100000, pos 00100000 21:33:54.955 -> 1162 mmu set 00110000, pos 00110000 21:33:54.990 -> 1162 mmu set 00120000, pos 00120000 21:33:54.990 -> 1162 mmu set 00130000, pos 00130000 21:33:54.990 -> 1162 mmu set 00140000, pos 00140000 21:33:54.990 -> 1162 mmu set 00150000, pos 00150000 21:33:55.023 -> 1162 mmu set 00160000, pos 00160000 21:33:55.023 -> 1162 mmu set 00170000, pos 00170000 21:33:55.023 -> 1162 mmu set 00180000, pos 00180000 21:33:55.056 -> 1162 mmu set 00190000, pos 00190000 21:33:55.056 -> 1162 mmu set 001a0000, pos 001a0000 21:33:55.056 -> 1162 mmu set 001b0000, pos 001b0000 21:33:55.056 -> 1162 mmu set 001c0000, pos 001c0000 21:33:55.092 -> 1162 mmu set 001d0000, pos 001d0000 21:33:55.092 -> 1162 mmu set 001e0000, pos 001e0000 21:33:55.092 -> 1162 mmu set 001f0000, pos 001f0000 21:33:55.129 -> ets Jun 8 2016 00:22:57 21:33:55.129 -> 21:33:55.129 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:55.129 -> configsip: 0, SPIWP:0xee 21:33:55.129 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:55.129 -> mode:DIO, clock div:1 21:33:55.129 -> load:0x3fff0018,len:4 21:33:55.129 -> load:0x3fff001c,len:192 21:33:55.129 -> ho 0 tail 12 room 4 21:33:55.129 -> load:0x725f4074,len:879902836 21:33:55.129 -> 1162 mmu set 00010000, pos 00010000 21:33:55.166 -> 1162 mmu set 00020000, pos 00020000 21:33:55.166 -> 1162 mmu set 00030000, pos 00030000 21:33:55.166 -> 1162 mmu set 00040000, pos 00040000 21:33:55.166 -> 1162 mmu set 00050000, pos 00050000 21:33:55.204 -> 1162 mmu set 00060000, pos 00060000 21:33:55.204 -> 1162 mmu set 00070000, pos 00070000 21:33:55.204 -> 1162 mmu set 00080000, pos 00080000 21:33:55.204 -> 1162 mmu set 00090000, pos 00090000 21:33:55.240 -> 1162 mmu set 000a0000, pos 000a0000 21:33:55.240 -> 1162 mmu set 000b0000, pos 000b0000 21:33:55.240 -> 1162 mmu set 000c0000, pos 000c0000 21:33:55.240 -> 1162 mmu set 000d0000, pos 000d0000 21:33:55.273 -> 1162 mmu set 000e0000, pos 000e0000 21:33:55.273 -> 1162 mmu set 000f0000, pos 000f0000 21:33:55.273 -> 1162 mmu set 00100000, pos 00100000 21:33:55.309 -> 1162 mmu set 00110000, pos 00110000 21:33:55.309 -> 1162 mmu set 00120000, pos 00120000 21:33:55.309 -> 1162 mmu set 00130000, pos 00130000 21:33:55.309 -> 1162 mmu set 00140000, pos 00140000 21:33:55.342 -> 1162 mmu set 00150000, pos 00150000 21:33:55.342 -> 1162 mmu set 00160000, pos 00160000 21:33:55.342 -> 1162 mmu set 00170000, pos 00170000 21:33:55.379 -> 1162 mmu set 00180000, pos 00180000 21:33:55.379 -> 1162 mmu set 00190000, pos 00190000 21:33:55.379 -> 1162 mmu set 001a0000, pos 001a0000 21:33:55.379 -> 1162 mmu set 001b0000, pos 001b0000 21:33:55.412 -> 1162 mmu set 001c0000, pos 001c0000 21:33:55.412 -> 1162 mmu set 001d0000, pos 001d0000 21:33:55.412 -> 1162 mmu set 001e0000, pos 001e0000 21:33:55.412 -> 1162 mmu set 001f0000, pos 001f0000 21:33:55.446 -> ets Jun 8 2016 00:22:57 21:33:55.446 -> 21:33:55.446 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:55.446 -> configsip: 0, SPIWP:0xee 21:33:55.446 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:55.446 -> mode:DIO, clock div:1 21:33:55.446 -> load:0x3fff0018,len:4 21:33:55.446 -> load:0x3fff001c,len:1216 21:33:55.446 -> ho 0 tail 12 room 4 21:33:55.446 -> load:0x40078000,len:10944 21:33:55.490 -> load:0x00080000,len:4340 21:33:55.757 -> ets Jun 8 2016 00:22:57 21:33:55.757 -> 21:33:55.757 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:55.757 -> configsip: 0, SPIWP:0xee 21:33:55.757 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:55.792 -> mode:DIO, clock div:1 21:33:55.792 -> load:0x3fff0018,len:4 21:33:55.792 -> load:0x3fff001c,len:1216 21:33:55.792 -> ho 0 tail 12 room 4 21:33:55.792 -> load:0x40078000,len:10944 21:33:55.792 -> load:0x00080000,len:4340 21:33:56.097 -> ets Jun 8 2016 00:22:57 21:33:56.097 -> 21:33:56.097 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:56.097 -> configsip: 0, SPIWP:0xee 21:33:56.097 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:56.097 -> mode:DIO, clock div:1 21:33:56.097 -> load:0x3fff0018,len:4 21:33:56.097 -> load:0x3fff001c,len:1216 21:33:56.097 -> ho 0 tail 12 room 4 21:33:56.097 -> load:0x40078000,len:10944 21:33:56.097 -> load:0x00080000,len:4340 21:33:56.406 -> ets Jun 8 2016 00:22:57 21:33:56.406 -> 21:33:56.406 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:56.448 -> configsip: 0, SPIWP:0xee 21:33:56.448 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:56.448 -> mode:DIO, clock div:1 21:33:56.448 -> load:0x3fff0018,len:4 21:33:56.448 -> load:0x3fff001c,len:1216 21:33:56.448 -> ho 0 tail 12 room 4 21:33:56.448 -> load:0x40078000,len:10944 21:33:56.448 -> load:0x00080000,len:4340 21:33:56.750 -> ets Jun 8 2016 00:22:57 21:33:56.750 -> 21:33:56.750 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:56.750 -> configsip: 0, SPIWP:0xee 21:33:56.750 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:56.750 -> mode:DIO, clock div:1 21:33:56.750 -> load:0x3fff0018,len:4 21:33:56.750 -> load:0x3fff001c,len:1216 21:33:56.750 -> ho 0 tail 12 room 4 21:33:56.750 -> load:0x40078000,len:10944 21:33:56.750 -> load:0x00080000,len:4340 21:33:57.058 -> ets Jun 8 2016 00:22:57 21:33:57.058 -> 21:33:57.058 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:57.058 -> configsip: 0, SPIWP:0xee 21:33:57.058 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:57.094 -> mode:DIO, clock div:1 21:33:57.094 -> load:0x3fff0018,len:4 21:33:57.094 -> load:0x3fff001c,len:1216 21:33:57.094 -> ho 0 tail 12 room 4 21:33:57.094 -> load:0x40078000,len:10944 21:33:57.094 -> load:0x00080000,len:4340 21:33:57.377 -> ets Jun 8 2016 00:22:57 21:33:57.454 -> 21:33:57.454 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:57.454 -> configsip: 0, SPIWP:0xee 21:33:57.454 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:57.454 -> mode:DIO, clock div:1 21:33:57.454 -> load:0x3fff0018,len:4 21:33:57.454 -> load:0x3fff001c,len:1216 21:33:57.454 -> ho 0 tail 12 room 4 21:33:57.454 -> load:0x40078000,len:10944 21:33:57.454 -> load:0x00080000,len:4340 21:33:57.722 -> ets Jun 8 2016 00:22:57 21:33:57.722 -> 21:33:57.722 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:57.722 -> configsip: 0, SPIWP:0xee 21:33:57.722 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:57.722 -> mode:DIO, clock div:1 21:33:57.722 -> load:0x3fff0018,len:4 21:33:57.722 -> load:0x3fff001c,len:1216 21:33:57.722 -> ho 0 tail 12 room 4 21:33:57.722 -> load:0x40078000,len:10944 21:33:57.722 -> load:0x00080000,len:4340 21:33:58.030 -> ets Jun 8 2016 00:22:57 21:33:58.030 -> 21:33:58.030 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:58.030 -> configsip: 0, SPIWP:0xee 21:33:58.064 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:58.064 -> mode:DIO, clock div:1 21:33:58.064 -> load:0x3fff0018,len:4 21:33:58.064 -> load:0x3fff001c,len:192 21:33:58.064 -> ho 0 tail 12 room 4 21:33:58.064 -> load:0x725f4074,len:879902836 21:33:58.064 -> 1162 mmu set 00010000, pos 00010000 21:33:58.064 -> 1162 mmu set 00020000, pos 00020000 21:33:58.098 -> 1162 mmu set 00030000, pos 00030000 21:33:58.098 -> 1162 mmu set 00040000, pos 00040000 21:33:58.098 -> 1162 mmu set 00050000, pos 00050000 21:33:58.098 -> 1162 mmu set 00060000, pos 00060000 21:33:58.132 -> 1162 mmu set 00070000, pos 00070000 21:33:58.132 -> 1162 mmu set 00080000, pos 00080000 21:33:58.132 -> 1162 mmu set 00090000, pos 00090000 21:33:58.168 -> 1162 mmu set 000a0000, pos 000a0000 21:33:58.168 -> 1162 mmu set 000b0000, pos 000b0000 21:33:58.168 -> 1162 mmu set 000c0000, pos 000c0000 21:33:58.168 -> 1162 mmu set 000d0000, pos 000d0000 21:33:58.204 -> 1162 mmu set 000e0000, pos 000e0000 21:33:58.204 -> 1162 mmu set 000f0000, pos 000f0000 21:33:58.204 -> 1162 mmu set 00100000, pos 00100000 21:33:58.204 -> 1162 mmu set 00110000, pos 00110000 21:33:58.238 -> 1162 mmu set 00120000, pos 00120000 21:33:58.238 -> 1162 mmu set 00130000, pos 00130000 21:33:58.238 -> 1162 mmu set 00140000, pos 00140000 21:33:58.238 -> 1162 mmu set 00150000, pos 00150000 21:33:58.275 -> 1162 mmu set 00160000, pos 00160000 21:33:58.275 -> 1162 mmu set 00170000, pos 00170000 21:33:58.275 -> 1162 mmu set 00180000, pos 00180000 21:33:58.309 -> 1162 mmu set 00190000, pos 00190000 21:33:58.309 -> 1162 mmu set 001a0000, pos 001a0000 21:33:58.309 -> 1162 mmu set 001b0000, pos 001b0000 21:33:58.309 -> 1162 mmu set 001c0000, pos 001c0000 21:33:58.346 -> 1162 mmu set 001d0000, pos 001d0000 21:33:58.346 -> 1162 mmu set 001e0000, pos 001e0000 21:33:58.346 -> 1162 mmu set 001f0000, pos 001f0000 21:33:58.346 -> ets Jun 8 2016 00:22:57 21:33:58.379 -> 21:33:58.379 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:58.379 -> configsip: 0, SPIWP:0xee 21:33:58.379 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:58.379 -> mode:DIO, clock div:1 21:33:58.379 -> load:0x3fff0018,len:4 21:33:58.379 -> load:0x3fff001c,len:1216 21:33:58.379 -> ho 0 tail 12 room 4 21:33:58.379 -> load:0x40078000,len:10944 21:33:58.379 -> load:0x00080000,len:4340 21:33:58.685 -> ets Jun 8 2016 00:22:57 21:33:58.685 -> 21:33:58.685 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:58.685 -> configsip: 0, SPIWP:0xee 21:33:58.685 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:58.720 -> mode:DIO, clock div:1 21:33:58.720 -> load:0x3fff0018,len:4 21:33:58.720 -> load:0x3fff001c,len:1216 21:33:58.720 -> ho 0 tail 12 room 4 21:33:58.720 -> load:0x40078000,len:10944 21:33:58.720 -> load:0x00080000,len:4340 21:33:59.034 -> ets Jun 8 2016 00:22:57 21:33:59.034 -> 21:33:59.034 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:59.034 -> configsip: 0, SPIWP:0xee 21:33:59.034 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:59.050 -> mode:DIO, clock div:1 21:33:59.050 -> load:0x3fff0018,len:4 21:33:59.050 -> load:0x3fff001c,len:1216 21:33:59.050 -> ho 0 tail 12 room 4 21:33:59.050 -> load:0x40078000,len:10944 21:33:59.050 -> load:0x00080000,len:4340 21:33:59.348 -> ets Jun 8 2016 00:22:57 21:33:59.348 -> 21:33:59.348 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:59.348 -> configsip: 0, SPIWP:0xee 21:33:59.348 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:59.348 -> mode:DIO, clock div:1 21:33:59.348 -> load:0x3fff0018,len:4 21:33:59.348 -> load:0x3fff001c,len:192 21:33:59.348 -> ho 0 tail 12 room 4 21:33:59.348 -> load:0x725f4074,len:879902836 21:33:59.348 -> 1162 mmu set 00010000, pos 00010000 21:33:59.382 -> 1162 mmu set 00020000, pos 00020000 21:33:59.382 -> 1162 mmu set 00030000, pos 00030000 21:33:59.382 -> 1162 mmu set 00040000, pos 00040000 21:33:59.419 -> 1162 mmu set 00050000, pos 00050000 21:33:59.419 -> 1162 mmu set 00060000, pos 00060000 21:33:59.419 -> 1162 mmu set 00070000, pos 00070000 21:33:59.419 -> 1162 mmu set 00080000, pos 00080000 21:33:59.452 -> 1162 mmu set 00090000, pos 00090000 21:33:59.452 -> 1162 mmu set 000a0000, pos 000a0000 21:33:59.452 -> 1162 mmu set 000b0000, pos 000b0000 21:33:59.490 -> 1162 mmu set 000c0000, pos 000c0000 21:33:59.490 -> 1162 mmu set 000d0000, pos 000d0000 21:33:59.490 -> 1162 mmu set 000e0000, pos 000e0000 21:33:59.490 -> 1162 mmu set 00⸮ets Jun 8 2016 00:22:57 21:33:59.490 -> 21:33:59.490 -> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:59.523 -> configsip: 0, SPIWP:0xee 21:33:59.523 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:59.523 -> mode:DIO, clock div:1 21:33:59.523 -> load:0x3fff0018,len:4 21:33:59.523 -> load:0x3fff001c,len:1216 21:33:59.523 -> ho 0 tail 12 room 4 21:33:59.523 -> load:0x40078000,len:10944 21:33:59.523 -> load:0x40080400,len:6388 21:33:59.523 -> entry 0x400806b4 21:33:59.523 -> ets Jun 8 2016 00:22:57 21:33:59.523 -> 21:33:59.523 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:59.523 -> configsip: 0, SPIWP:0xee 21:33:59.557 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:59.557 -> mode:DIO, clock div:1 21:33:59.557 -> load:0x3fff0018,len:4 21:33:59.557 -> load:0x3fff001c,len:1216 21:33:59.557 -> ho 0 tail 12 room 4 21:33:59.557 -> load:0x40078000,len:10944 21:33:59.557 -> load:0x00080000,len:4340 21:33:59.874 -> ets Jun 8 2016 00:22:57 21:33:59.874 -> 21:33:59.874 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:33:59.874 -> configsip: 0, SPIWP:0xee 21:33:59.874 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:33:59.874 -> mode:DIO, clock div:1 21:33:59.874 -> load:0x3fff0018,len:4 21:33:59.874 -> load:0x3fff001c,len:1216 21:33:59.874 -> ho 0 tail 12 room 4 21:33:59.874 -> load:0x40078000,len:10944 21:33:59.874 -> load:0x00080000,len:4340 21:34:00.198 -> ets Jun 8 2016 00:22:57 21:34:00.198 -> 21:34:00.198 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:00.198 -> configsip: 0, SPIWP:0xee 21:34:00.198 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:00.198 -> mode:DIO, clock div:1 21:34:00.198 -> load:0x3fff0018,len:4 21:34:00.198 -> load:0x3fff001c,len:1216 21:34:00.198 -> ho 0 tail 12 room 4 21:34:00.198 -> load:0x40078000,len:10944 21:34:00.198 -> load:0x00080000,len:4340 21:34:00.514 -> ets Jun 8 2016 00:22:57 21:34:00.514 -> 21:34:00.514 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:00.514 -> configsip: 0, SPIWP:0xee 21:34:00.514 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:00.514 -> mode:DIO, clock div:1 21:34:00.514 -> load:0x3fff0018,len:4 21:34:00.514 -> load:0x3fff001c,len:1216 21:34:00.514 -> ho 0 tail 12 room 4 21:34:00.547 -> load:0x40078000,len:10944 21:34:00.547 -> load:0x00080000,len:4340 21:34:00.820 -> ets Jun 8 2016 00:22:57 21:34:00.820 -> 21:34:00.820 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:00.856 -> configsip: 0, SPIWP:0xee 21:34:00.856 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:00.856 -> mode:DIO, clock div:1 21:34:00.856 -> load:0x3fff0018,len:4 21:34:00.856 -> load:0x3fff001c,len:1216 21:34:00.856 -> ho 0 tail 12 room 4 21:34:00.856 -> load:0x40078000,len:10944 21:34:00.856 -> load:0x00080000,len:4340 21:34:01.164 -> ets Jun 8 2016 00:22:57 21:34:01.164 -> 21:34:01.164 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:01.164 -> configsip: 0, SPIWP:0xee 21:34:01.164 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:01.164 -> mode:DIO, clock div:1 21:34:01.164 -> load:0x3fff0018,len:4 21:34:01.164 -> load:0x3fff001c,len:1216 21:34:01.164 -> ho 0 tail 12 room 4 21:34:01.164 -> load:0x40078000,len:10944 21:34:01.198 -> load:0x00080000,len:4340 21:34:01.472 -> ets Jun 8 2016 00:22:57 21:34:01.472 -> 21:34:01.472 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:01.509 -> configsip: 0, SPIWP:0xee 21:34:01.509 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:01.509 -> mode:DIO, clock div:1 21:34:01.509 -> load:0x3fff0018,len:4 21:34:01.509 -> load:0x3fff001c,len:1216 21:34:01.509 -> ho 0 tail 12 room 4 21:34:01.509 -> load:0x40078000,len:10944 21:34:01.509 -> load:0x00080000,len:4340 21:34:01.822 -> ets Jun 8 2016 00:22:57 21:34:01.822 -> 21:34:01.822 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:01.822 -> configsip: 0, SPIWP:0xee 21:34:01.822 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:01.822 -> mode:DIO, clock div:1 21:34:01.822 -> load:0x3fff0018,len:4 21:34:01.822 -> load:0x3fff001c,len:1216 21:34:01.822 -> ho 0 tail 12 room 4 21:34:01.822 -> load:0x40078000,len:10944 21:34:01.822 -> load:0x00080000,len:4340 21:34:02.133 -> ets Jun 8 2016 00:22:57 21:34:02.133 -> 21:34:02.133 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:02.133 -> configsip: 0, SPIWP:0xee 21:34:02.133 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:02.133 -> mode:DIO, clock div:1 21:34:02.133 -> load:0x3fff0018,len:4 21:34:02.168 -> load:0x3fff001c,len:192 21:34:02.168 -> ho 0 tail 12 room 4 21:34:02.168 -> load:0x725f4074,len:879902836 21:34:02.168 -> 1162 mmu set 00010000, pos 00010000 21:34:02.168 -> 1162 mmu set 00020000, pos 00020000 21:34:02.168 -> 1162 mmu set 00030000, pos 00030000 21:34:02.204 -> 1162 mmu set 00040000, pos 00040000 21:34:02.204 -> 1162 mmu set 00050000, pos 00050000 21:34:02.204 -> 1162 mmu set 00060000, pos 00060000 21:34:02.204 -> 1162 mmu set 00070000, pos 00070000 21:34:02.238 -> 1162 mmu set 00080000, pos 00080000 21:34:02.238 -> 1162 mmu set 00090000, pos 00090000 21:34:02.238 -> 1162 mmu set 000a0000, pos 000a0000 21:34:02.238 -> 1162 mmu set 000b0000, pos 000b0000 21:34:02.272 -> 1162 mmu set 000c0000, pos 000c0000 21:34:02.272 -> 1162 mmu set 000d0000, pos 000d0000 21:34:02.272 -> 1162 mmu set 000e0000, pos 000e0000 21:34:02.339 -> 1162 mmu set 000f0000, pos 000f0000 21:34:02.339 -> 1162 mmu set 00100000, pos 00100000 21:34:02.339 -> 1162 mmu set 00110000, pos 00110000 21:34:02.339 -> 1162 mmu set 00120000, pos 00120000 21:34:02.339 -> 1162 mmu set 00130000, pos 00130000 21:34:02.384 -> 1162 mmu set 00140000, pos 00140000 21:34:02.384 -> 1162 mmu set 00150000, pos 00150000 21:34:02.384 -> 1162 mmu set 00160000, pos 00160000 21:34:02.384 -> 1162 mmu set 00170000, pos 00170000 21:34:02.395 -> 1162 mmu set 00180000, pos 00180000 21:34:02.395 -> 1162 mmu set 00190000, pos 00190000 21:34:02.395 -> 1162 mmu set 001a0000, pos 001a0000 21:34:02.458 -> 1162 mmu set 001b0000, pos 001b0000 21:34:02.458 -> 1162 mmu set 001c0000, pos 001c0000 21:34:02.458 -> 1162 mmu set 001d0000, pos 001d0000 21:34:02.458 -> 1162 mmu set 001e0000, pos 001e0000 21:34:02.458 -> 1162 mmu set 001f0000, pos 001f0000 21:34:02.483 -> ets Jun 8 2016 00:22:57 21:34:02.483 -> 21:34:02.483 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:02.483 -> configsip: 0, SPIWP:0xee 21:34:02.483 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:02.483 -> mode:DIO, clock div:1 21:34:02.483 -> load:0x3fff0018,len:4 21:34:02.483 -> load:0x3fff001c,len:1216 21:34:02.483 -> ho 0 tail 12 room 4 21:34:02.483 -> load:0x40078000,len:10944 21:34:02.483 -> load:0x00080000,len:4340 21:34:02.772 -> ets Jun 8 2016 00:22:57 21:34:02.772 -> 21:34:02.772 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:02.809 -> configsip: 0, SPIWP:0xee 21:34:02.809 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:02.809 -> mode:DIO, clock div:1 21:34:02.809 -> load:0x3fff0018,len:4 21:34:02.809 -> load:0x3fff001c,len:1216 21:34:02.809 -> ho 0 tail 12 room 4 21:34:02.809 -> load:0x40078000,len:10944 21:34:02.809 -> load:0x00080000,len:4340 21:34:03.118 -> ets Jun 8 2016 00:22:57 21:34:03.118 -> 21:34:03.118 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:03.118 -> configsip: 0, SPIWP:0xee 21:34:03.118 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:03.118 -> mode:DIO, clock div:1 21:34:03.118 -> load:0x3fff0018,len:4 21:34:03.118 -> load:0x3fff001c,len:1216 21:34:03.118 -> ho 0 tail 12 room 4 21:34:03.118 -> load:0x40078000,len:10944 21:34:03.118 -> load:0x00080000,len:4340 21:34:03.462 -> ets Jun 8 2016 00:22:57 21:34:03.462 -> 21:34:03.462 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:03.462 -> configsip: 0, SPIWP:0xee 21:34:03.462 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:03.484 -> mode:DIO, clock div:1 21:34:03.484 -> load:0x3fff0018,len:4 21:34:03.484 -> load:0x3fff001c,len:1216 21:34:03.484 -> ho 0 tail 12 room 4 21:34:03.484 -> load:0x40078000,len:10944 21:34:03.484 -> load:0x00080000,len:4340 21:34:03.747 -> ets Jun 8 2016 00:22:57 21:34:03.747 -> 21:34:03.747 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:03.747 -> configsip: 0, SPIWP:0xee 21:34:03.782 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:03.782 -> mode:DIO, clock div:1 21:34:03.782 -> load:0x3fff0018,len:4 21:34:03.782 -> load:0x3fff001c,len:1216 21:34:03.782 -> ho 0 tail 12 room 4 21:34:03.782 -> load:0x40078000,len:10944 21:34:03.782 -> load:0x00080000,len:4340 21:34:04.091 -> ets Jun 8 2016 00:22:57 21:34:04.091 -> 21:34:04.091 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:04.091 -> configsip: 0, SPIWP:0xee 21:34:04.091 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:04.091 -> mode:DIO, clock div:1 21:34:04.091 -> load:0x3fff0018,len:4 21:34:04.091 -> load:0x3fff001c,len:1216 21:34:04.091 -> ho 0 tail 12 room 4 21:34:04.091 -> load:0x40078000,len:10944 21:34:04.126 -> load:0x00080000,len:4340 21:34:04.417 -> ets Jun 8 2016 00:22:57 21:34:04.417 -> 21:34:04.417 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:04.417 -> configsip: 0, SPIWP:0xee 21:34:04.417 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:04.456 -> mode:DIO, clock div:1 21:34:04.456 -> load:0x3fff0018,len:4 21:34:04.456 -> load:0x3fff001c,len:1216 21:34:04.456 -> ho 0 tail 12 room 4 21:34:04.456 -> load:0x40078000,len:10944 21:34:04.456 -> load:0x00080000,len:4340 21:34:04.742 -> ets Jun 8 2016 00:22:57 21:34:04.742 -> 21:34:04.742 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:04.742 -> configsip: 0, SPIWP:0xee 21:34:04.742 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:04.742 -> mode:DIO, clock div:1 21:34:04.742 -> load:0x3fff0018,len:4 21:34:04.742 -> load:0x3fff001c,len:1216 21:34:04.742 -> ho 0 tail 12 room 4 21:34:04.742 -> load:0x40078000,len:10944 21:34:04.742 -> load:0x00080000,len:4340 21:34:05.051 -> ets Jun 8 2016 00:22:57 21:34:05.051 -> 21:34:05.051 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:05.051 -> configsip: 0, SPIWP:0xee 21:34:05.051 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:05.084 -> mode:DIO, clock div:1 21:34:05.084 -> load:0x3fff0018,len:4 21:34:05.084 -> load:0x3fff001c,len:1216 21:34:05.084 -> ho 0 tail 12 room 4 21:34:05.084 -> load:0x40078000,len:10944 21:34:05.084 -> load:0x00080000,len:4340 21:34:05.391 -> ets Jun 8 2016 00:22:57 21:34:05.391 -> 21:34:05.391 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:05.391 -> configsip: 0, SPIWP:0xee 21:34:05.391 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:05.391 -> mode:DIO, clock div:1 21:34:05.391 -> load:0x3fff0018,len:4 21:34:05.391 -> load:0x3fff001c,len:1216 21:34:05.391 -> ho 0 tail 12 room 4 21:34:05.391 -> load:0x40078000,len:10944 21:34:05.424 -> load:0x00080000,len:4340 21:34:05.699 -> ets Jun 8 2016 00:22:57 21:34:05.699 -> 21:34:05.699 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:05.699 -> configsip: 0, SPIWP:0xee 21:34:05.699 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:05.736 -> mode:DIO, clock div:1 21:34:05.736 -> load:0x3fff0018,len:4 21:34:05.736 -> load:0x3fff001c,len:1216 21:34:05.736 -> ho 0 tail 12 room 4 21:34:05.736 -> load:0x40078000,len:10944 21:34:05.736 -> load:0x00080000,len:4340 21:34:06.015 -> ets Jun 8 2016 00:22:57 21:34:06.048 -> 21:34:06.048 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:06.048 -> configsip: 0, SPIWP:0xee 21:34:06.048 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:06.048 -> mode:DIO, clock div:1 21:34:06.048 -> load:0x3fff0018,len:4 21:34:06.048 -> load:0x3fff001c,len:1216 21:34:06.048 -> ho 0 tail 12 room 4 21:34:06.048 -> load:0x40078000,len:10944 21:34:06.048 -> load:0x00080000,len:4340 21:34:06.364 -> ets Jun 8 2016 00:22:57 21:34:06.364 -> 21:34:06.364 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:06.364 -> configsip: 0, SPIWP:0xee 21:34:06.364 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:06.364 -> mode:DIO, clock div:1 21:34:06.364 -> load:0x3fff0018,len:4 21:34:06.364 -> load:0x3fff001c,len:1216 21:34:06.364 -> ho 0 tail 12 room 4 21:34:06.402 -> load:0x40078000,len:10944 21:34:06.402 -> load:0x00080000,len:4340 21:34:06.676 -> ets Jun 8 2016 00:22:57 21:34:06.676 -> 21:34:06.676 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:06.676 -> configsip: 0, SPIWP:0xee 21:34:06.676 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:06.713 -> mode:DIO, clock div:1 21:34:06.713 -> load:0x3fff0018,len:4 21:34:06.713 -> load:0x3fff001c,len:1216 21:34:06.713 -> ho 0 tail 12 room 4 21:34:06.713 -> load:0x40078000,len:10944 21:34:06.713 -> load:0x00080000,len:4340 21:34:07.016 -> ets Jun 8 2016 00:22:57 21:34:07.016 -> 21:34:07.016 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:07.016 -> configsip: 0, SPIWP:0xee 21:34:07.016 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:07.016 -> mode:DIO, clock div:1 21:34:07.016 -> load:0x3fff0018,len:4 21:34:07.016 -> load:0x3fff001c,len:1216 21:34:07.016 -> ho 0 tail 12 room 4 21:34:07.050 -> load:0x40078000,len:10944 21:34:07.050 -> load:0x00080000,len:4340 21:34:07.317 -> ets Jun 8 2016 00:22:57 21:34:07.353 -> 21:34:07.353 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:07.353 -> configsip: 0, SPIWP:0xee 21:34:07.353 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:07.353 -> mode:DIO, clock div:1 21:34:07.353 -> load:0x3fff0018,len:4 21:34:07.353 -> load:0x3fff001c,len:1216 21:34:07.353 -> ho 0 tail 12 room 4 21:34:07.353 -> load:0x40078000,len:10944 21:34:07.353 -> load:0x00080000,len:4340 21:34:07.657 -> ets Jun 8 2016 00:22:57 21:34:07.657 -> 21:34:07.657 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:07.657 -> configsip: 0, SPIWP:0xee 21:34:07.657 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:07.691 -> mode:DIO, clock div:1 21:34:07.691 -> load:0x3fff0018,len:4 21:34:07.691 -> load:0x3fff001c,len:192 21:34:07.691 -> ho 0 tail 12 room 4 21:34:07.691 -> load:0x725f4074,len:879902836 21:34:07.691 -> 1162 mmu set 00010000, pos 00010000 21:34:07.691 -> 1162 mmu set 00020000, pos 00020000 21:34:07.691 -> 1162 mmu set 00030000, pos 00030000 21:34:07.724 -> 1162 mmu set 00040000, pos 00040000 21:34:07.724 -> 1162 mmu set 00050000, pos 00050000 21:34:07.724 -> 1162 mmu set 00060000, pos 00060000 21:34:07.724 -> 1162 mmu set 00070000, pos 00070000 21:34:07.758 -> 1162 mmu set 00080000, pos 00080000 21:34:07.758 -> 1162 mmu set 00090000, pos 00090000 21:34:07.758 -> 1162 mmu set 000a0000, pos 000a0000 21:34:07.791 -> 1162 mmu set 000b0000, pos 000b0000 21:34:07.791 -> 1162 mmu set 000c0000, pos 000c0000 21:34:07.791 -> 1162 mmu set 000d0000, pos 000d0000 21:34:07.824 -> 1162 mmu set 000e0000, pos 000e0000 21:34:07.824 -> 1162 mmu set 000f0000, pos 0⸮ets Jun 8 2016 00:22:57 21:34:07.824 -> 21:34:07.824 -> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:07.824 -> configsip: 0, SPIWP:0xee 21:34:07.824 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:07.824 -> mode:DIO, clock div:1 21:34:07.824 -> load:0x3fff0018,len:4 21:34:07.868 -> load:0x3fff001c,len:1216 21:34:07.868 -> ho 0 tail 12 room 4 21:34:07.868 -> load:0x40078000,len:10944 21:34:07.868 -> load:0x40080400,len:6388 21:34:07.868 -> entry 0x400806b4 21:34:07.868 -> ets Jun 8 2016 00:22:57 21:34:07.868 -> 21:34:07.868 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:07.868 -> configsip: 0, SPIWP:0xee 21:34:07.868 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:07.868 -> mode:DIO, clock div:1 21:34:07.868 -> load:0x3fff0018,len:4 21:34:07.868 -> load:0x3fff001c,len:1216 21:34:07.868 -> ho 0 tail 12 room 4 21:34:07.868 -> load:0x40078000,len:10944 21:34:07.868 -> load:0x00080000,len:4340 21:34:08.167 -> ets Jun 8 2016 00:22:57 21:34:08.167 -> 21:34:08.167 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:08.204 -> configsip: 0, SPIWP:0xee 21:34:08.204 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:08.204 -> mode:DIO, clock div:1 21:34:08.204 -> load:0x3fff0018,len:4 21:34:08.204 -> load:0x3fff001c,len:192 21:34:08.204 -> ho 0 tail 12 room 4 21:34:08.204 -> load:0x725f4074,len:879902836 21:34:08.204 -> 1162 mmu set 00010000, pos 00010000 21:34:08.204 -> 1162 mmu set 00020000, pos 00020000 21:34:08.241 -> 1162 mmu set 00030000, pos 00030000 21:34:08.241 -> 1162 mmu set 00040000, pos 00040000 21:34:08.241 -> 1162 mmu set 00050000, pos 00050000 21:34:08.241 -> 1162 mmu set 00060000, pos 00060000 21:34:08.277 -> 1162 mmu set 00070000, pos 00070000 21:34:08.277 -> 1162 mmu set 00080000, pos 00080000 21:34:08.277 -> 1162 mmu set 00090000, pos 00090000 21:34:08.277 -> 1162 mmu set 000a0000, pos 000a0000 21:34:08.313 -> 1162 mmu set 000b0000, pos 000b0000 21:34:08.313 -> 1162 mmu set 000c0000, pos 000c0000 21:34:08.313 -> 1162 mmu set 000d0000, pos 000d0000 21:34:08.313 -> 1162 mmu set 000e0000, pos 000e0000 21:34:08.347 -> 1162 mmu set 000f0000, pos 000f0000 21:34:08.347 -> 1162 mmu set 00100000, pos 00100000 21:34:08.347 -> 1162 mmu set 00110000, pos 00110000 21:34:08.380 -> 1162 mmu set 00120000, pos 00120000 21:34:08.380 -> 1162 mmu set 00130000, pos 00130000 21:34:08.380 -> 1162 mmu set 00140000, pos 00140000 21:34:08.380 -> 1162 mmu set 00150000, pos 00150000 21:34:08.413 -> 1162 mmu set 00160000, pos 00160000 21:34:08.413 -> 1162 mmu set 00170000, pos 00170000 21:34:08.413 -> 1162 mmu set 00180000, pos 00180000 21:34:08.446 -> 1162 mmu set 00190000, pos 00190000 21:34:08.446 -> 1162 mmu set 001a0000, pos 001a0000 21:34:08.446 -> 1162 mmu set 001b0000, pos 001b0000 21:34:08.481 -> 1162 mmu set 001c0000, pos 001c0000 21:34:08.481 -> 1162 mmu set 001d0000, pos 001d0000 21:34:08.481 -> 1162 mmu set 001e0000, pos 001e0000 21:34:08.481 -> 1162 mmu set 001f0000, pos 001f0000 21:34:08.514 -> ets Jun 8 2016 00:22:57 21:34:08.514 -> 21:34:08.514 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:08.514 -> configsip: 0, SPIWP:0xee 21:34:08.514 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:08.514 -> mode:DIO, clock div:1 21:34:08.514 -> load:0x3fff0018,len:4 21:34:08.514 -> load:0x3fff001c,len:1216 21:34:08.514 -> ho 0 tail 12 room 4 21:34:08.514 -> load:0x40078000,len:10944 21:34:08.514 -> load:0x00080000,len:4340 21:34:08.818 -> ets Jun 8 2016 00:22:57 21:34:08.818 -> 21:34:08.818 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:08.852 -> configsip: 0, SPIWP:0xee 21:34:08.852 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:08.852 -> mode:DIO, clock div:1 21:34:08.852 -> load:0x3fff0018,len:4 21:34:08.852 -> load:0x3fff001c,len:1216 21:34:08.852 -> ho 0 tail 12 room 4 21:34:08.852 -> load:0x40078000,len:10944 21:34:08.852 -> load:0x00080000,len:4340 21:34:09.158 -> ets Jun 8 2016 00:22:57 21:34:09.158 -> 21:34:09.158 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:09.158 -> configsip: 0, SPIWP:0xee 21:34:09.158 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:09.158 -> mode:DIO, clock div:1 21:34:09.158 -> load:0x3fff0018,len:4 21:34:09.158 -> load:0x3fff001c,len:1216 21:34:09.193 -> ho 0 tail 12 room 4 21:34:09.193 -> load:0x40078000,len:10944 21:34:09.193 -> load:0x00080000,len:4340 21:34:09.463 -> ets Jun 8 2016 00:22:57 21:34:09.497 -> 21:34:09.497 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:09.497 -> configsip: 0, SPIWP:0xee 21:34:09.497 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:09.497 -> mode:DIO, clock div:1 21:34:09.497 -> load:0x3fff0018,len:4 21:34:09.497 -> load:0x3fff001c,len:1216 21:34:09.497 -> ho 0 tail 12 room 4 21:34:09.497 -> load:0x40078000,len:10944 21:34:09.497 -> load:0x00080000,len:4340 21:34:09.822 -> ets Jun 8 2016 00:22:57 21:34:09.822 -> 21:34:09.822 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:09.822 -> configsip: 0, SPIWP:0xee 21:34:09.822 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:09.822 -> mode:DIO, clock div:1 21:34:09.822 -> load:0x3fff0018,len:4 21:34:09.822 -> load:0x3fff001c,len:1216 21:34:09.822 -> ho 0 tail 12 room 4 21:34:09.822 -> load:0x40078000,len:10944 21:34:09.822 -> load:0x00080000,len:4340 21:34:10.132 -> ets Jun 8 2016 00:22:57 21:34:10.132 -> 21:34:10.132 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:10.132 -> configsip: 0, SPIWP:0xee 21:34:10.132 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:10.132 -> mode:DIO, clock div:1 21:34:10.132 -> load:0x3fff0018,len:4 21:34:10.132 -> load:0x3fff001c,len:1216 21:34:10.167 -> ho 0 tail 12 room 4 21:34:10.167 -> load:0x40078000,len:10944 21:34:10.167 -> load:0x00080000,len:4340 21:34:10.450 -> ets Jun 8 2016 00:22:57 21:34:10.450 -> 21:34:10.450 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:10.450 -> configsip: 0, SPIWP:0xee 21:34:10.450 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:10.487 -> mode:DIO, clock div:1 21:34:10.487 -> load:0x3fff0018,len:4 21:34:10.487 -> load:0x3fff001c,len:1216 21:34:10.487 -> ho 0 tail 12 room 4 21:34:10.487 -> load:0x40078000,len:10944 21:34:10.487 -> load:0x00080000,len:4340 21:34:10.775 -> ets Jun 8 2016 00:22:57 21:34:10.775 -> 21:34:10.775 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:10.775 -> configsip: 0, SPIWP:0xee 21:34:10.817 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:10.817 -> mode:DIO, clock div:1 21:34:10.817 -> load:0x3fff0018,len:4 21:34:10.817 -> load:0x3fff001c,len:1216 21:34:10.817 -> ho 0 tail 12 room 4 21:34:10.817 -> load:0x40078000,len:10944 21:34:10.817 -> load:0x00080000,len:4340 21:34:11.092 -> ets Jun 8 2016 00:22:57 21:34:11.092 -> 21:34:11.092 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:11.125 -> configsip: 0, SPIWP:0xee 21:34:11.125 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:11.125 -> mode:DIO, clock div:1 21:34:11.125 -> load:0x3fff0018,len:4 21:34:11.125 -> load:0x3fff001c,len:1216 21:34:11.125 -> ho 0 tail 12 room 4 21:34:11.125 -> load:0x40078000,len:10944 21:34:11.125 -> load:0x00080000,len:4340 21:34:11.432 -> ets Jun 8 2016 00:22:57 21:34:11.432 -> 21:34:11.432 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:11.432 -> configsip: 0, SPIWP:0xee 21:34:11.432 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:11.432 -> mode:DIO, clock div:1 21:34:11.432 -> load:0x3fff0018,len:4 21:34:11.465 -> load:0x3fff001c,len:1216 21:34:11.465 -> ho 0 tail 12 room 4 21:34:11.465 -> load:0x40078000,len:10944 21:34:11.465 -> load:0x00080000,len:4340 21:34:11.746 -> ets Jun 8 2016 00:22:57 21:34:11.746 -> 21:34:11.746 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:11.816 -> configsip: 0, SPIWP:0xee 21:34:11.816 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:11.816 -> mode:DIO, clock div:1 21:34:11.816 -> load:0x3fff0018,len:4 21:34:11.816 -> load:0x3fff001c,len:192 21:34:11.816 -> ho 0 tail 12 room 4 21:34:11.816 -> load:0x725f4074,len:879902836 21:34:11.816 -> 1162 mmu set 00010000, pos 00010000 21:34:11.816 -> 1162 mmu set 00020000, pos 00020000 21:34:11.816 -> 1162 mmu set 00030000, pos 00030000 21:34:11.816 -> 1162 mmu set 00040000, pos 00040000 21:34:11.836 -> 1162 mmu set 00050000, pos 00050000 21:34:11.836 -> 1162 mmu set 00060000, pos 00060000 21:34:11.836 -> 1162 mmu set 00070000, pos 00070000 21:34:11.903 -> 1162 mmu set 00080000, pos 00080000 21:34:11.903 -> 1162 mmu set 00090000, pos 00090000 21:34:11.903 -> 1162 mmu set 000a0000, pos 000a0000 21:34:11.903 -> 1162 mmu set 000b0000, pos 000b0000 21:34:11.903 -> 1162 mmu set 000c0000, pos 000c0000 21:34:11.952 -> 1162 mmu set 000d0000, pos 000d0000 21:34:11.952 -> 1162 mmu set 000e0000, pos 000e0000 21:34:11.952 -> 1162 mmu set 000f0000, pos 000f0000 21:34:11.952 -> 1162 mmu set 00100000, pos 00100000 21:34:11.959 -> 1162 mmu set 00110000, pos 00110000 21:34:11.959 -> 1162 mmu set 00120000, pos 00120000 21:34:11.959 -> 1162 mmu set 00130000, pos 00130000 21:34:11.959 -> 1162 mmu set 00140000, pos 00140000 21:34:11.973 -> 1162 mmu set 00150000, pos 00150000 21:34:12.088 -> 1162 mmu set 00160000, pos 00160000 21:34:12.088 -> 1162 mmu set 00170000, pos 00170000 21:34:12.088 -> 1162 mmu set 00180000, pos 00180000 21:34:12.088 -> 1162 mmu set 00190000, pos 00190000 21:34:12.088 -> 1162 mmu set 001a0000, pos 001a0000 21:34:12.088 -> 1162 mmu set 001b0000, pos 001b0000 21:34:12.088 -> 1162 mmu set 001c0000, pos 001c0000 21:34:12.105 -> 1162 mmu set 001d0000, pos 001d0000 21:34:12.105 -> 1162 mmu set 001e0000, pos 001e0000 21:34:12.105 -> 1162 mmu set 001f0000, pos 001f0000 21:34:12.105 -> ets Jun 8 2016 00:22:57 21:34:12.105 -> 21:34:12.105 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:12.105 -> configsip: 0, SPIWP:0xee 21:34:12.105 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:12.105 -> mode:DIO, clock div:1 21:34:12.105 -> load:0x3fff0018,len:4 21:34:12.138 -> load:0x3fff001c,len:1216 21:34:12.138 -> ho 0 tail 12 room 4 21:34:12.138 -> load:0x40078000,len:10944 21:34:12.138 -> load:0x00080000,len:4340 21:34:12.423 -> ets Jun 8 2016 00:22:57 21:34:12.423 -> 21:34:12.423 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:12.423 -> configsip: 0, SPIWP:0xee 21:34:12.423 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:12.423 -> mode:DIO, clock div:1 21:34:12.423 -> load:0x3fff0018,len:4 21:34:12.423 -> load:0x3fff001c,len:1216 21:34:12.423 -> ho 0 tail 12 room 4 21:34:12.423 -> load:0x40078000,len:10944 21:34:12.423 -> load:0x00080000,len:4340 21:34:12.723 -> ets Jun 8 2016 00:22:57 21:34:12.723 -> 21:34:12.723 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:12.723 -> configsip: 0, SPIWP:0xee 21:34:12.723 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:12.757 -> mode:DIO, clock div:1 21:34:12.757 -> load:0x3fff0018,len:4 21:34:12.757 -> load:0x3fff001c,len:1216 21:34:12.757 -> ho 0 tail 12 room 4 21:34:12.757 -> load:0x40078000,len:10944 21:34:12.757 -> load:0x00080000,len:4340 21:34:13.036 -> ets Jun 8 2016 00:22:57 21:34:13.098 -> 21:34:13.098 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:13.098 -> configsip: 0, SPIWP:0xee 21:34:13.098 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:13.098 -> mode:DIO, clock div:1 21:34:13.098 -> load:0x3fff0018,len:4 21:34:13.098 -> load:0x3fff001c,len:1216 21:34:13.098 -> ho 0 tail 12 room 4 21:34:13.098 -> load:0x40078000,len:10944 21:34:13.098 -> load:0x00080000,len:4340 21:34:13.381 -> ets Jun 8 2016 00:22:57 21:34:13.381 -> 21:34:13.381 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:13.381 -> configsip: 0, SPIWP:0xee 21:34:13.381 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:13.381 -> mode:DIO, clock div:1 21:34:13.381 -> load:0x3fff0018,len:4 21:34:13.420 -> load:0x3fff001c,len:1216 21:34:13.420 -> ho 0 tail 12 room 4 21:34:13.420 -> load:0x40078000,len:10944 21:34:13.420 -> load:0x00080000,len:4340 21:34:13.697 -> ets Jun 8 2016 00:22:57 21:34:13.697 -> 21:34:13.697 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:13.697 -> configsip: 0, SPIWP:0xee 21:34:13.730 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:13.730 -> mode:DIO, clock div:1 21:34:13.730 -> load:0x3fff0018,len:4 21:34:13.730 -> load:0x3fff001c,len:1216 21:34:13.730 -> ho 0 tail 12 room 4 21:34:13.730 -> load:0x40078000,len:10944 21:34:13.730 -> load:0x00080000,len:4340 21:34:14.039 -> ets Jun 8 2016 00:22:57 21:34:14.039 -> 21:34:14.039 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:14.039 -> configsip: 0, SPIWP:0xee 21:34:14.039 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:14.039 -> mode:DIO, clock div:1 21:34:14.039 -> load:0x3fff0018,len:4 21:34:14.039 -> load:0x3fff001c,len:192 21:34:14.039 -> ho 0 tail 12 room 4 21:34:14.039 -> load:0x725f4074,len:879902836 21:34:14.039 -> 1162 mmu set 00010000, pos 00010000 21:34:14.074 -> 1162 mmu set 00020000, pos 00020000 21:34:14.074 -> 1162 mmu set 00030000, pos 00030000 21:34:14.074 -> 1162 mmu set 00040000, pos 00040000 21:34:14.074 -> 1162 mmu set 00050000, pos 00050000 21:34:14.110 -> 1162 mmu set 00060000, pos 00060000 21:34:14.110 -> 1162 mmu set 00070000, pos 00070000 21:34:14.110 -> 1162 mmu set 00080000, pos 00080000 21:34:14.185 -> 1162 mmu set 00090000, pos 00090000 21:34:14.185 -> 1162 mmu set 000a0000, pos 000a0000 21:34:14.185 -> 1162 mmu set 000b0000, pos 000b0000 21:34:14.185 -> 1162 mmu set 000c0000, pos 000c0000 21:34:14.185 -> 1162 mmu set 000d0000, pos 000d0000 21:34:14.237 -> 1162 mmu set 000e0000, pos 000e0000 21:34:14.237 -> 1162 mmu set 000f0000, pos 000f0000 21:34:14.237 -> 1162 mmu set 00100000, pos 00100000 21:34:14.237 -> 1162 mmu set 00110000, pos 00110000 21:34:14.284 -> 1162 mmu set 00120000, pos 00120000 21:34:14.284 -> 1162 mmu set 00130000, pos 00130000 21:34:14.284 -> 1162 mmu set 00140000, pos 00140000 21:34:14.284 -> 1162 mmu set 00150000, pos 00150000 21:34:14.284 -> 1162 mmu set 00160000, pos 00160000 21:34:14.303 -> 1162 mmu set 00170000, pos 00170000 21:34:14.303 -> 1162 mmu set 00180000, pos 00180000 21:34:14.303 -> 1162 mmu set 00190000, pos 00190000 21:34:14.303 -> 1162 mmu set 001a0000, pos 001a0000 21:34:14.322 -> 1162 mmu set 001b0000, pos 001b0000 21:34:14.388 -> 1162 mmu set 001c0000, pos 001c0000 21:34:14.388 -> 1162 mmu set 001d0000, pos 001d0000 21:34:14.388 -> 1162 mmu set 001e0000, pos 001e0000 21:34:14.388 -> 1162 mmu set 001f0000, pos 001f0000 21:34:14.388 -> ets Jun 8 2016 00:22:57 21:34:14.388 -> 21:34:14.388 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:14.388 -> configsip: 0, SPIWP:0xee 21:34:14.388 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:14.426 -> mode:DIO, clock div:1 21:34:14.426 -> load:0x3fff0018,len:4 21:34:14.426 -> load:0x3fff001c,len:1216 21:34:14.426 -> ho 0 tail 12 room 4 21:34:14.426 -> load:0x40078000,len:10944 21:34:14.426 -> load:0x00080000,len:4340 21:34:14.673 -> ets Jun 8 2016 00:22:57 21:34:14.690 -> 21:34:14.690 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:14.690 -> configsip: 0, SPIWP:0xee 21:34:14.690 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:14.690 -> mode:DIO, clock div:1 21:34:14.690 -> load:0x3fff0018,len:4 21:34:14.690 -> load:0x3fff001c,len:1216 21:34:14.690 -> ho 0 tail 12 room 4 21:34:14.690 -> load:0x40078000,len:10944 21:34:14.690 -> load:0x00080000,len:4340 21:34:14.999 -> ets Jun 8 2016 00:22:57 21:34:14.999 -> 21:34:14.999 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:14.999 -> configsip: 0, SPIWP:0xee 21:34:14.999 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:15.037 -> mode:DIO, clock div:1 21:34:15.037 -> load:0x3fff0018,len:4 21:34:15.037 -> load:0x3fff001c,len:1216 21:34:15.037 -> ho 0 tail 12 room 4 21:34:15.037 -> load:0x40078000,len:10944 21:34:15.037 -> load:0x00080000,len:4340 21:34:15.318 -> ets Jun 8 2016 00:22:57 21:34:15.318 -> 21:34:15.318 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:15.355 -> configsip: 0, SPIWP:0xee 21:34:15.355 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:15.355 -> mode:DIO, clock div:1 21:34:15.355 -> load:0x3fff0018,len:4 21:34:15.355 -> load:0x3fff001c,len:1216 21:34:15.355 -> ho 0 tail 12 room 4 21:34:15.355 -> load:0x40078000,len:10944 21:34:15.355 -> load:0x00080000,len:4340 21:34:15.666 -> ets Jun 8 2016 00:22:57 21:34:15.666 -> 21:34:15.666 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:15.666 -> configsip: 0, SPIWP:0xee 21:34:15.666 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:15.666 -> mode:DIO, clock div:1 21:34:15.666 -> load:0x3fff0018,len:4 21:34:15.666 -> load:0x3fff001c,len:1216 21:34:15.666 -> ho 0 tail 12 room 4 21:34:15.666 -> load:0x40078000,len:10944 21:34:15.666 -> load:0x00080000,len:4340 21:34:15.977 -> ets Jun 8 2016 00:22:57 21:34:15.977 -> 21:34:15.977 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:15.977 -> configsip: 0, SPIWP:0xee 21:34:15.977 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:16.051 -> mode:DIO, clock div:1 21:34:16.051 -> load:0x3fff0018,len:4 21:34:16.051 -> load:0x3fff001c,len:1216 21:34:16.051 -> ho 0 tail 12 room 4 21:34:16.051 -> load:0x40078000,len:10944 21:34:16.051 -> load:0x00080000,len:4340 21:34:16.142 -> ets Jun 8 2016 00:22:57 21:34:16.196 -> 21:34:16.196 -> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:16.196 -> configsip: 0, SPIWP:0xee 21:34:16.196 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:16.196 -> mode:DIO, clock div:1 21:34:16.196 -> load:0x3fff0018,len:4 21:34:16.196 -> load:0x3fff001c,len:1216 21:34:16.196 -> ho 0 tail 12 room 4 21:34:16.196 -> load:0x40078000,len:10944 21:34:16.196 -> load:0x40080400,len:6388 21:34:16.196 -> entry 0x400806b4 21:34:16.196 -> ets Jun 8 2016 00:22:57 21:34:16.196 -> 21:34:16.196 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:16.196 -> configsip: 0, SPIWP:0xee 21:34:16.196 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:16.196 -> mode:DIO, clock div:1 21:34:16.242 -> load:0x3fff0018,len:4 21:34:16.242 -> load:0x3fff001c,len:1216 21:34:16.242 -> ho 0 tail 12 room 4 21:34:16.242 -> load:0x40078000,len:10944 21:34:16.242 -> load:0x00080000,len:4340 21:34:16.486 -> ets Jun 8 2016 00:22:57 21:34:16.520 -> 21:34:16.520 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:16.520 -> configsip: 0, SPIWP:0xee 21:34:16.520 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:16.520 -> mode:DIO, clock div:1 21:34:16.520 -> load:0x3fff0018,len:4 21:34:16.520 -> load:0x3fff001c,len:1216 21:34:16.520 -> ho 0 tail 12 room 4 21:34:16.520 -> load:0x40078000,len:10944 21:34:16.520 -> load:0x00080000,len:4340 21:34:16.821 -> ets Jun 8 2016 00:22:57 21:34:16.821 -> 21:34:16.821 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:16.821 -> configsip: 0, SPIWP:0xee 21:34:16.821 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:16.854 -> mode:DIO, clock div:1 21:34:16.854 -> load:0x3fff0018,len:4 21:34:16.854 -> load:0x3fff001c,len:1216 21:34:16.854 -> ho 0 tail 12 room 4 21:34:16.854 -> load:0x40078000,len:10944 21:34:16.854 -> load:0x00080000,len:4340 21:34:17.159 -> ets Jun 8 2016 00:22:57 21:34:17.159 -> 21:34:17.159 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:17.159 -> configsip: 0, SPIWP:0xee 21:34:17.159 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:17.159 -> mode:DIO, clock div:1 21:34:17.159 -> load:0x3fff0018,len:4 21:34:17.159 -> load:0x3fff001c,len:1216 21:34:17.159 -> ho 0 tail 12 room 4 21:34:17.159 -> load:0x40078000,len:10944 21:34:17.192 -> load:0x00080000,len:4340 21:34:17.463 -> ets Jun 8 2016 00:22:57 21:34:17.463 -> 21:34:17.463 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:17.498 -> configsip: 0, SPIWP:0xee 21:34:17.498 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:17.498 -> mode:DIO, clock div:1 21:34:17.498 -> load:0x3fff0018,len:4 21:34:17.498 -> load:0x3fff001c,len:1216 21:34:17.498 -> ho 0 tail 12 room 4 21:34:17.498 -> load:0x40078000,len:10944 21:34:17.498 -> load:0x00080000,len:4340 21:34:17.787 -> ets Jun 8 2016 00:22:57 21:34:17.833 -> 21:34:17.833 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:17.833 -> configsip: 0, SPIWP:0xee 21:34:17.833 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:17.833 -> mode:DIO, clock div:1 21:34:17.833 -> load:0x3fff0018,len:4 21:34:17.833 -> load:0x3fff001c,len:1216 21:34:17.833 -> ho 0 tail 12 room 4 21:34:17.833 -> load:0x40078000,len:10944 21:34:17.833 -> load:0x00080000,len:4340 21:34:18.153 -> ets Jun 8 2016 00:22:57 21:34:18.153 -> 21:34:18.153 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:18.153 -> configsip: 0, SPIWP:0xee 21:34:18.153 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:18.153 -> mode:DIO, clock div:1 21:34:18.153 -> load:0x3fff0018,len:4 21:34:18.153 -> load:0x3fff001c,len:1216 21:34:18.153 -> ho 0 tail 12 room 4 21:34:18.153 -> load:0x40078000,len:10944 21:34:18.153 -> load:0x00080000,len:4340 21:34:18.469 -> ets Jun 8 2016 00:22:57 21:34:18.469 -> 21:34:18.469 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:18.478 -> configsip: 0, SPIWP:0xee 21:34:18.478 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:18.478 -> mode:DIO, clock div:1 21:34:18.478 -> load:0x3fff0018,len:4 21:34:18.478 -> load:0x3fff001c,len:1216 21:34:18.478 -> ho 0 tail 12 room 4 21:34:18.478 -> load:0x40078000,len:10944 21:34:18.478 -> load:0x00080000,len:4340 21:34:18.784 -> ets Jun 8 2016 00:22:57 21:34:18.784 -> 21:34:18.784 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:18.784 -> configsip: 0, SPIWP:0xee 21:34:18.784 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:18.784 -> mode:DIO, clock div:1 21:34:18.784 -> load:0x3fff0018,len:4 21:34:18.784 -> load:0x3fff001c,len:1216 21:34:18.784 -> ho 0 tail 12 room 4 21:34:18.817 -> load:0x40078000,len:10944 21:34:18.817 -> load:0x00080000,len:4340 21:34:19.085 -> ets Jun 8 2016 00:22:57 21:34:19.120 -> 21:34:19.120 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:19.120 -> configsip: 0, SPIWP:0xee 21:34:19.120 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:19.120 -> mode:DIO, clock div:1 21:34:19.120 -> load:0x3fff0018,len:4 21:34:19.120 -> load:0x3fff001c,len:1216 21:34:19.120 -> ho 0 tail 12 room 4 21:34:19.120 -> load:0x40078000,len:10944 21:34:19.120 -> load:0x00080000,len:4340 21:34:19.430 -> ets Jun 8 2016 00:22:57 21:34:19.430 -> 21:34:19.430 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:19.430 -> configsip: 0, SPIWP:0xee 21:34:19.430 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:19.430 -> mode:DIO, clock div:1 21:34:19.430 -> load:0x3fff0018,len:4 21:34:19.430 -> load:0x3fff001c,len:1216 21:34:19.467 -> ho 0 tail 12 room 4 21:34:19.467 -> load:0x40078000,len:10944 21:34:19.467 -> load:0x00080000,len:4340 21:34:19.738 -> ets Jun 8 2016 00:22:57 21:34:19.738 -> 21:34:19.738 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:19.771 -> configsip: 0, SPIWP:0xee 21:34:19.771 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:19.771 -> mode:DIO, clock div:1 21:34:19.771 -> load:0x3fff0018,len:4 21:34:19.771 -> load:0x3fff001c,len:1216 21:34:19.771 -> ho 0 tail 12 room 4 21:34:19.771 -> load:0x40078000,len:10944 21:34:19.771 -> load:0x00080000,len:4340 21:34:20.082 -> ets Jun 8 2016 00:22:57 21:34:20.082 -> 21:34:20.082 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:20.082 -> configsip: 0, SPIWP:0xee 21:34:20.082 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:20.082 -> mode:DIO, clock div:1 21:34:20.082 -> load:0x3fff0018,len:4 21:34:20.082 -> load:0x3fff001c,len:1216 21:34:20.082 -> ho 0 tail 12 room 4 21:34:20.115 -> load:0x40078000,len:10944 21:34:20.115 -> load:0x00080000,len:4340 21:34:20.389 -> ets Jun 8 2016 00:22:57 21:34:20.389 -> 21:34:20.389 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:20.426 -> configsip: 0, SPIWP:0xee 21:34:20.426 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:20.426 -> mode:DIO, clock div:1 21:34:20.426 -> load:0x3fff0018,len:4 21:34:20.426 -> load:0x3fff001c,len:1216 21:34:20.426 -> ho 0 tail 12 room 4 21:34:20.426 -> load:0x40078000,len:10944 21:34:20.426 -> load:0x00080000,len:4340 21:34:20.732 -> ets Jun 8 2016 00:22:57 21:34:20.732 -> 21:34:20.732 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:20.732 -> configsip: 0, SPIWP:0xee 21:34:20.732 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:20.732 -> mode:DIO, clock div:1 21:34:20.732 -> load:0x3fff0018,len:4 21:34:20.732 -> load:0x3fff001c,len:192 21:34:20.732 -> ho 0 tail 12 room 4 21:34:20.766 -> load:0x725f4074,len:879902836 21:34:20.766 -> 1162 mmu set 00010000, pos 00010000 21:34:20.766 -> 1162 mmu set 00020000, pos 00020000 21:34:20.766 -> 1162 mmu set 00030000, pos 00030000 21:34:20.766 -> 1162 mmu set 00040000, pos 00040000 21:34:20.799 -> 1162 mmu set 00050000, pos 00050000 21:34:20.799 -> 1162 mmu set 00060000, pos 00060000 21:34:20.799 -> 1162 mmu set 00070000, pos 00070000 21:34:20.833 -> 1162 mmu set 00080000, pos 00080000 21:34:20.833 -> 1162 mmu set 00090000, pos 00090000 21:34:20.833 -> 1162 mmu set 000a0000, pos 000a0000 21:34:20.833 -> 1162 mmu set 000b0000, pos 000b0000 21:34:20.867 -> 1162 mmu set 000c0000, pos 000c0000 21:34:20.867 -> 1162 mmu set 000d0000, pos 000d0000 21:34:20.867 -> 1162 mmu set 000e0000, pos 000e0000 21:34:20.900 -> 1162 mmu set 000f0000, pos 000f0000 21:34:20.900 -> 1162 mmu set 00100000, pos 00100000 21:34:20.900 -> 1162 mmu set 00110000, pos 00110000 21:34:20.900 -> 1162 mmu set 00120000, pos 00120000 21:34:20.933 -> 1162 mmu set 00130000, pos 00130000 21:34:20.933 -> 1162 mmu set 00140000, pos 00140000 21:34:20.933 -> 1162 mmu set 00150000, pos 00150000 21:34:20.970 -> 1162 mmu set 00160000, pos 00160000 21:34:20.970 -> 1162 mmu set 00170000, pos 00170000 21:34:20.970 -> 1162 mmu set 00180000, pos 00180000 21:34:20.970 -> 1162 mmu set 00190000, pos 00190000 21:34:21.004 -> 1162 mmu set 001a0000, pos 001a0000 21:34:21.004 -> 1162 mmu set 001b0000, pos 001b0000 21:34:21.004 -> 1162 mmu set 001c0000, pos 001c0000 21:34:21.037 -> 1162 mmu set 001d0000, pos 001d0000 21:34:21.037 -> 1162 mmu set 001e0000, pos 001e0000 21:34:21.037 -> 1162 mmu set 001f0000, pos 001f0000 21:34:21.037 -> ets Jun 8 2016 00:22:57 21:34:21.037 -> 21:34:21.037 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:21.074 -> configsip: 0, SPIWP:0xee 21:34:21.074 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:21.074 -> mode:DIO, clock div:1 21:34:21.074 -> load:0x3fff0018,len:4 21:34:21.074 -> load:0x3fff001c,len:1216 21:34:21.074 -> ho 0 tail 12 room 4 21:34:21.074 -> load:0x40078000,len:10944 21:34:21.074 -> load:0x00080000,len:4340 21:34:21.390 -> ets Jun 8 2016 00:22:57 21:34:21.390 -> 21:34:21.390 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:21.390 -> configsip: 0, SPIWP:0xee 21:34:21.390 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:21.390 -> mode:DIO, clock div:1 21:34:21.390 -> load:0x3fff0018,len:4 21:34:21.390 -> load:0x3fff001c,len:1216 21:34:21.390 -> ho 0 tail 12 room 4 21:34:21.390 -> load:0x40078000,len:10944 21:34:21.390 -> load:0x00080000,len:4340 21:34:21.700 -> ets Jun 8 2016 00:22:57 21:34:21.700 -> 21:34:21.700 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:21.700 -> configsip: 0, SPIWP:0xee 21:34:21.700 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:21.700 -> mode:DIO, clock div:1 21:34:21.734 -> load:0x3fff0018,len:4 21:34:21.734 -> load:0x3fff001c,len:1216 21:34:21.734 -> ho 0 tail 12 room 4 21:34:21.734 -> load:0x40078000,len:10944 21:34:21.734 -> load:0x00080000,len:4340 21:34:22.040 -> ets Jun 8 2016 00:22:57 21:34:22.040 -> 21:34:22.040 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:22.040 -> configsip: 0, SPIWP:0xee 21:34:22.040 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:22.040 -> mode:DIO, clock div:1 21:34:22.040 -> load:0x3fff0018,len:4 21:34:22.040 -> load:0x3fff001c,len:1216 21:34:22.040 -> ho 0 tail 12 room 4 21:34:22.040 -> load:0x40078000,len:10944 21:34:22.040 -> load:0x00080000,len:4340 21:34:22.347 -> ets Jun 8 2016 00:22:57 21:34:22.347 -> 21:34:22.347 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:22.347 -> configsip: 0, SPIWP:0xee 21:34:22.347 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:22.380 -> mode:DIO, clock div:1 21:34:22.380 -> load:0x3fff0018,len:4 21:34:22.380 -> load:0x3fff001c,len:1216 21:34:22.380 -> ho 0 tail 12 room 4 21:34:22.380 -> load:0x40078000,len:10944 21:34:22.380 -> load:0x00080000,len:4340 21:34:22.683 -> ets Jun 8 2016 00:22:57 21:34:22.683 -> 21:34:22.683 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:22.683 -> configsip: 0, SPIWP:0xee 21:34:22.683 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:22.683 -> mode:DIO, clock div:1 21:34:22.683 -> load:0x3fff0018,len:4 21:34:22.683 -> load:0x3fff001c,len:1216 21:34:22.683 -> ho 0 tail 12 room 4 21:34:22.717 -> load:0x40078000,len:10944 21:34:22.717 -> load:0x00080000,len:4340 21:34:22.990 -> ets Jun 8 2016 00:22:57 21:34:22.990 -> 21:34:22.990 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:23.023 -> configsip: 0, SPIWP:0xee 21:34:23.023 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:23.023 -> mode:DIO, clock div:1 21:34:23.023 -> load:0x3fff0018,len:4 21:34:23.023 -> load:0x3fff001c,len:192 21:34:23.023 -> ho 0 tail 12 room 4 21:34:23.023 -> load:0x725f4074,len:879902836 21:34:23.023 -> 1162 mmu set 00010000, pos 00010000 21:34:23.023 -> 1162 mmu set 00020000, pos 00020000 21:34:23.060 -> 1162 mmu set 00030000, pos 00030000 21:34:23.060 -> 1162 mmu set 00040000, pos 00040000 21:34:23.060 -> 1162 mmu set 00050000, pos 00050000 21:34:23.060 -> 1162 mmu set 00060000, pos 00060000 21:34:23.097 -> 1162 mmu set 00070000, pos 00070000 21:34:23.097 -> 1162 mmu set 00080000, pos 00080000 21:34:23.097 -> 1162 mmu set 00090000, pos 00090000 21:34:23.097 -> 1162 mmu set 000a0000, pos 000a0000 21:34:23.130 -> 1162 mmu set 000b0000, pos 000b0000 21:34:23.130 -> 1162 mmu set 000c0000, pos 000c0000 21:34:23.130 -> 1162 mmu set 000d0000, pos 000d0000 21:34:23.163 -> 1162 mmu set 000e0000, pos 000e0000 21:34:23.163 -> 1162 mmu set 000f0000, pos 000f0000 21:34:23.163 -> 1162 mmu set 00100000, pos 00100000 21:34:23.197 -> 1162 mmu set 00110000, pos 00110000 21:34:23.197 -> 1162 mmu set 00120000, pos 00120000 21:34:23.197 -> 1162 mmu set 00130000, pos 00130000 21:34:23.197 -> 1162 mmu set 00140000, pos 00140000 21:34:23.230 -> 1162 mmu set 00150000, pos 00150000 21:34:23.230 -> 1162 mmu set 00160000, pos 00160000 21:34:23.230 -> 1162 mmu set 00170000, pos 00170000 21:34:23.264 -> 1162 mmu set 00180000, pos 00180000 21:34:23.264 -> 1162 mmu set 00190000, pos 00190000 21:34:23.264 -> 1162 mmu set 001a0000, pos 001a0000 21:34:23.264 -> 1162 mmu set 001b0000, pos 001b0000 21:34:23.297 -> 1162 mmu set 001c0000, pos 001c0000 21:34:23.297 -> 1162 mmu set 001d0000, pos 001d0000 21:34:23.297 -> 1162 mmu set 001e0000, pos 001e0000 21:34:23.330 -> 1162 mmu set 001f0000, pos 001f0000 21:34:23.330 -> ets Jun 8 2016 00:22:57 21:34:23.330 -> 21:34:23.330 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:23.330 -> configsip: 0, SPIWP:0xee 21:34:23.330 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:23.330 -> mode:DIO, clock div:1 21:34:23.330 -> load:0x3fff0018,len:4 21:34:23.330 -> load:0x3fff001c,len:1216 21:34:23.364 -> ho 0 tail 12 room 4 21:34:23.364 -> load:0x40078000,len:10944 21:34:23.364 -> load:0x00080000,len:4340 21:34:23.643 -> ets Jun 8 2016 00:22:57 21:34:23.643 -> 21:34:23.643 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:23.677 -> configsip: 0, SPIWP:0xee 21:34:23.677 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:23.677 -> mode:DIO, clock div:1 21:34:23.677 -> load:0x3fff0018,len:4 21:34:23.677 -> load:0x3fff001c,len:1216 21:34:23.677 -> ho 0 tail 12 room 4 21:34:23.677 -> load:0x40078000,len:10944 21:34:23.677 -> load:0x00080000,len:4340 21:34:24.024 -> ets Jun 8 2016 00:22:57 21:34:24.024 -> 21:34:24.024 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:24.046 -> configsip: 0, SPIWP:0xee 21:34:24.046 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:24.046 -> mode:DIO, clock div:1 21:34:24.046 -> load:0x3fff0018,len:4 21:34:24.046 -> load:0x3fff001c,len:1216 21:34:24.046 -> ho 0 tail 12 room 4 21:34:24.046 -> load:0x40078000,len:10944 21:34:24.046 -> load:0x00080000,len:4340 21:34:24.354 -> ets Jun 8 2016 00:22:57 21:34:24.354 -> 21:34:24.354 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:24.354 -> configsip: 0, SPIWP:0xee 21:34:24.354 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:24.354 -> mode:DIO, clock div:1 21:34:24.354 -> load:0x3fff0018,len:4 21:34:24.354 -> load:0x3fff001c,len:1216 21:34:24.354 -> ho 0 tail 12 room 4 21:34:24.354 -> load:0x40078000,len:10944 21:34:24.354 -> load:0x00080000,len:4340 21:34:24.459 -> ets Jun 8 2016 00:22:57 21:34:24.459 -> 21:34:24.459 -> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:24.459 -> configsip: 0, SPIWP:0xee 21:34:24.495 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:24.495 -> mode:DIO, clock div:1 21:34:24.495 -> load:0x3fff0018,len:4 21:34:24.495 -> load:0x3fff001c,len:1216 21:34:24.495 -> ho 0 tail 12 room 4 21:34:24.495 -> load:0x40078000,len:10944 21:34:24.495 -> load:0x40080400,len:6388 21:34:24.495 -> entry 0x400806b4 21:34:24.495 -> ets Jun 8 2016 00:22:57 21:34:24.495 -> 21:34:24.495 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:24.495 -> configsip: 0, SPIWP:0xee 21:34:24.495 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:24.531 -> mode:DIO, clock div:1 21:34:24.531 -> load:0x3fff0018,len:4 21:34:24.531 -> load:0x3fff001c,len:1216 21:34:24.531 -> ho 0 tail 12 room 4 21:34:24.531 -> load:0x40078000,len:10944 21:34:24.531 -> load:0x00080000,len:4340 21:34:24.835 -> ets Jun 8 2016 00:22:57 21:34:24.835 -> 21:34:24.835 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:24.835 -> configsip: 0, SPIWP:0xee 21:34:24.835 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:24.835 -> mode:DIO, clock div:1 21:34:24.835 -> load:0x3fff0018,len:4 21:34:24.835 -> load:0x3fff001c,len:192 21:34:24.835 -> ho 0 tail 12 room 4 21:34:24.835 -> load:0x725f4074,len:879902836 21:34:24.835 -> 1162 mmu set 00010000, pos 00010000 21:34:24.872 -> 1162 mmu set 00020000, pos 00020000 21:34:24.872 -> 1162 mmu set 00030000, pos 00030000 21:34:24.872 -> 1162 mmu set 00040000, pos 00040000 21:34:24.872 -> 1162 mmu set 00050000, pos 00050000 21:34:24.906 -> 1162 mmu set 00060000, pos 00060000 21:34:24.906 -> 1162 mmu set 00070000, pos 00070000 21:34:24.906 -> 1162 mmu set 00080000, pos 00080000 21:34:24.942 -> 1162 mmu set 00090000, pos 00090000 21:34:24.942 -> 1162 mmu set 000a0000, pos 000a0000 21:34:24.942 -> 1162 mmu set 000b0000, pos 000b0000 21:34:24.942 -> 1162 mmu set 000c0000, pos 000c0000 21:34:24.976 -> 1162 mmu set 000d0000, pos 000d0000 21:34:24.976 -> 1162 mmu set 000e0000, pos 000e0000 21:34:24.976 -> 1162 mmu set 000f0000, pos 000f0000 21:34:25.010 -> 1162 mmu set 00100000, pos 00100000 21:34:25.010 -> 1162 mmu set 00110000, pos 00110000 21:34:25.010 -> 1162 mmu set 00120000, pos 00120000 21:34:25.010 -> 1162 mmu set 00130000, pos 00130000 21:34:25.043 -> 1162 mmu set 00140000, pos 00140000 21:34:25.043 -> 1162 mmu set 00150000, pos 00150000 21:34:25.043 -> 1162 mmu set 00160000, pos 00160000 21:34:25.081 -> 1162 mmu set 00170000, pos 00170000 21:34:25.081 -> 1162 mmu set 00180000, pos 00180000 21:34:25.081 -> 1162 mmu set 00190000, pos 00190000 21:34:25.081 -> 1162 mmu set 001a0000, pos 001a0000 21:34:25.118 -> 1162 mmu set 001b0000, pos 001b0000 21:34:25.118 -> 1162 mmu set 001c0000, pos 001c0000 21:34:25.118 -> 1162 mmu set 001d0000, pos 001d0000 21:34:25.118 -> 1162 mmu set 001e0000, pos 001e0000 21:34:25.154 -> 1162 mmu set 001f0000, pos 001f0000 21:34:25.154 -> ets Jun 8 2016 00:22:57 21:34:25.154 -> 21:34:25.154 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:25.154 -> configsip: 0, SPIWP:0xee 21:34:25.154 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:25.154 -> mode:DIO, clock div:1 21:34:25.154 -> load:0x3fff0018,len:4 21:34:25.154 -> load:0x3fff001c,len:1216 21:34:25.154 -> ho 0 tail 12 room 4 21:34:25.188 -> load:0x40078000,len:10944 21:34:25.188 -> load:0x00080000,len:4340 21:34:25.458 -> ets Jun 8 2016 00:22:57 21:34:25.458 -> 21:34:25.458 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:25.492 -> configsip: 0, SPIWP:0xee 21:34:25.492 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:25.492 -> mode:DIO, clock div:1 21:34:25.492 -> load:0x3fff0018,len:4 21:34:25.492 -> load:0x3fff001c,len:1216 21:34:25.492 -> ho 0 tail 12 room 4 21:34:25.492 -> load:0x40078000,len:10944 21:34:25.492 -> load:0x00080000,len:4340 21:34:25.828 -> ets Jun 8 2016 00:22:57 21:34:25.828 -> 21:34:25.828 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:25.828 -> configsip: 0, SPIWP:0xee 21:34:25.828 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:25.828 -> mode:DIO, clock div:1 21:34:25.828 -> load:0x3fff0018,len:4 21:34:25.828 -> load:0x3fff001c,len:1216 21:34:25.828 -> ho 0 tail 12 room 4 21:34:25.828 -> load:0x40078000,len:10944 21:34:25.828 -> load:0x00080000,len:4340 21:34:26.125 -> ets Jun 8 2016 00:22:57 21:34:26.125 -> 21:34:26.125 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:26.125 -> configsip: 0, SPIWP:0xee 21:34:26.125 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:26.125 -> mode:DIO, clock div:1 21:34:26.159 -> load:0x3fff0018,len:4 21:34:26.159 -> load:0x3fff001c,len:1216 21:34:26.159 -> ho 0 tail 12 room 4 21:34:26.159 -> load:0x40078000,len:10944 21:34:26.159 -> load:0x00080000,len:4340 21:34:26.432 -> ets Jun 8 2016 00:22:57 21:34:26.465 -> 21:34:26.465 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:26.465 -> configsip: 0, SPIWP:0xee 21:34:26.465 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:26.465 -> mode:DIO, clock div:1 21:34:26.465 -> load:0x3fff0018,len:4 21:34:26.465 -> load:0x3fff001c,len:192 21:34:26.465 -> ho 0 tail 12 room 4 21:34:26.465 -> load:0x725f4074,len:879902836 21:34:26.465 -> 1162 mmu set 00010000, pos 00010000 21:34:26.465 -> 1162 mmu set 00020000, pos 00020000 21:34:26.498 -> 1162 mmu set 00030000, pos 00030000 21:34:26.498 -> 1162 mmu set 00040000, pos 00040000 21:34:26.498 -> 1162 mmu set 00050000, pos 00050000 21:34:26.532 -> 1162 mmu set 00060000, pos 00060000 21:34:26.532 -> 1162 mmu set 00070000, pos 00070000 21:34:26.532 -> 1162 mmu set 00080000, pos 00080000 21:34:26.569 -> 1162 mmu set 00090000, pos 00090000 21:34:26.569 -> 1162 mmu set 000a0000, pos 000a0000 21:34:26.569 -> 1162 mmu set 000b0000, pos 000b0000 21:34:26.569 -> 1162 mmu set 000c0000, pos 000c0000 21:34:26.603 -> 1162 mmu set 000d0000, pos 000d0000 21:34:26.603 -> 1162 mmu set 000e0000, pos 000e0000 21:34:26.603 -> 1162 mmu set 000f0000, pos 000f0000 21:34:26.603 -> 1162 mmu set 00100000, pos 00100000 21:34:26.636 -> 1162 mmu set 00110000, pos 00110000 21:34:26.636 -> 1162 mmu set 00120000, pos 00120000 21:34:26.636 -> 1162 mmu set 00130000, pos 00130000 21:34:26.669 -> 1162 mmu set 00140000, pos 00140000 21:34:26.669 -> 1162 mmu set 00150000, pos 00150000 21:34:26.669 -> 1162 mmu set 00160000, pos 00160000 21:34:26.669 -> 1162 mmu set 00170000, pos 00170000 21:34:26.705 -> 1162 mmu set 00180000, pos 00180000 21:34:26.705 -> 1162 mmu set 00190000, pos 00190000 21:34:26.705 -> 1162 mmu set 001a0000, pos 001a0000 21:34:26.738 -> 1162 mmu set 001b0000, pos 001b0000 21:34:26.738 -> 1162 mmu set 001c0000, pos 001c0000 21:34:26.738 -> 1162 mmu set 001d0000, pos 001d0000 21:34:26.738 -> 1162 mmu set 001e0000, pos 001e0000 21:34:26.771 -> 1162 mmu set 001f0000, pos 001f0000 21:34:26.771 -> ets Jun 8 2016 00:22:57 21:34:26.771 -> 21:34:26.771 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:26.771 -> configsip: 0, SPIWP:0xee 21:34:26.771 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:26.805 -> mode:DIO, clock div:1 21:34:26.805 -> load:0x3fff0018,len:4 21:34:26.805 -> load:0x3fff001c,len:1216 21:34:26.805 -> ho 0 tail 12 room 4 21:34:26.805 -> load:0x40078000,len:10944 21:34:26.805 -> load:0x00080000,len:4340 21:34:27.092 -> ets Jun 8 2016 00:22:57 21:34:27.092 -> 21:34:27.092 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:27.125 -> configsip: 0, SPIWP:0xee 21:34:27.125 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:27.125 -> mode:DIO, clock div:1 21:34:27.125 -> load:0x3fff0018,len:4 21:34:27.125 -> load:0x3fff001c,len:1216 21:34:27.125 -> ho 0 tail 12 room 4 21:34:27.125 -> load:0x40078000,len:10944 21:34:27.125 -> load:0x00080000,len:4340 21:34:27.410 -> ets Jun 8 2016 00:22:57 21:34:27.410 -> 21:34:27.410 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:27.443 -> configsip: 0, SPIWP:0xee 21:34:27.443 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:27.443 -> mode:DIO, clock div:1 21:34:27.443 -> load:0x3fff0018,len:4 21:34:27.443 -> load:0x3fff001c,len:1216 21:34:27.443 -> ho 0 tail 12 room 4 21:34:27.443 -> load:0x40078000,len:10944 21:34:27.443 -> load:0x00080000,len:4340 21:34:27.753 -> ets Jun 8 2016 00:22:57 21:34:27.753 -> 21:34:27.753 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:27.753 -> configsip: 0, SPIWP:0xee 21:34:27.753 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:27.753 -> mode:DIO, clock div:1 21:34:27.753 -> load:0x3fff0018,len:4 21:34:27.753 -> load:0x3fff001c,len:1216 21:34:27.786 -> ho 0 tail 12 room 4 21:34:27.786 -> load:0x40078000,len:10944 21:34:27.786 -> load:0x00080000,len:4340 21:34:28.059 -> ets Jun 8 2016 00:22:57 21:34:28.059 -> 21:34:28.059 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:28.093 -> configsip: 0, SPIWP:0xee 21:34:28.093 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:28.093 -> mode:DIO, clock div:1 21:34:28.093 -> load:0x3fff0018,len:4 21:34:28.093 -> load:0x3fff001c,len:1216 21:34:28.093 -> ho 0 tail 12 room 4 21:34:28.093 -> load:0x40078000,len:10944 21:34:28.093 -> load:0x00080000,len:4340 21:34:28.405 -> ets Jun 8 2016 00:22:57 21:34:28.405 -> 21:34:28.405 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:28.405 -> configsip: 0, SPIWP:0xee 21:34:28.405 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:28.405 -> mode:DIO, clock div:1 21:34:28.405 -> load:0x3fff0018,len:4 21:34:28.405 -> load:0x3fff001c,len:1216 21:34:28.405 -> ho 0 tail 12 room 4 21:34:28.440 -> load:0x40078000,len:10944 21:34:28.440 -> load:0x00080000,len:4340 21:34:28.714 -> ets Jun 8 2016 00:22:57 21:34:28.714 -> 21:34:28.714 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:28.714 -> configsip: 0, SPIWP:0xee 21:34:28.748 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:28.748 -> mode:DIO, clock div:1 21:34:28.748 -> load:0x3fff0018,len:4 21:34:28.748 -> load:0x3fff001c,len:1216 21:34:28.748 -> ho 0 tail 12 room 4 21:34:28.748 -> load:0x40078000,len:10944 21:34:28.748 -> load:0x00080000,len:4340 21:34:29.050 -> ets Jun 8 2016 00:22:57 21:34:29.050 -> 21:34:29.050 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:29.050 -> configsip: 0, SPIWP:0xee 21:34:29.050 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:29.050 -> mode:DIO, clock div:1 21:34:29.050 -> load:0x3fff0018,len:4 21:34:29.084 -> load:0x3fff001c,len:1216 21:34:29.084 -> ho 0 tail 12 room 4 21:34:29.084 -> load:0x40078000,len:10944 21:34:29.084 -> load:0x00080000,len:4340 21:34:29.368 -> ets Jun 8 2016 00:22:57 21:34:29.368 -> 21:34:29.368 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:29.368 -> configsip: 0, SPIWP:0xee 21:34:29.368 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:29.403 -> mode:DIO, clock div:1 21:34:29.403 -> load:0x3fff0018,len:4 21:34:29.403 -> load:0x3fff001c,len:1216 21:34:29.403 -> ho 0 tail 12 room 4 21:34:29.403 -> load:0x40078000,len:10944 21:34:29.403 -> load:0x00080000,len:4340 21:34:29.715 -> ets Jun 8 2016 00:22:57 21:34:29.715 -> 21:34:29.715 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:29.715 -> configsip: 0, SPIWP:0xee 21:34:29.715 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:29.715 -> mode:DIO, clock div:1 21:34:29.715 -> load:0x3fff0018,len:4 21:34:29.715 -> load:0x3fff001c,len:1216 21:34:29.715 -> ho 0 tail 12 room 4 21:34:29.715 -> load:0x40078000,len:10944 21:34:29.715 -> load:0x00080000,len:4340 21:34:30.024 -> ets Jun 8 2016 00:22:57 21:34:30.024 -> 21:34:30.024 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:30.024 -> configsip: 0, SPIWP:0xee 21:34:30.024 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:30.024 -> mode:DIO, clock div:1 21:34:30.062 -> load:0x3fff0018,len:4 21:34:30.062 -> load:0x3fff001c,len:192 21:34:30.062 -> ho 0 tail 12 room 4 21:34:30.062 -> load:0x725f4074,len:879902836 21:34:30.062 -> 1162 mmu set 00010000, pos 00010000 21:34:30.062 -> 1162 mmu set 00020000, pos 00020000 21:34:30.062 -> 1162 mmu set 00030000, pos 00030000 21:34:30.062 -> 1162 mmu set 00040000, pos 00040000 21:34:30.097 -> 1162 mmu set 00050000, pos 00050000 21:34:30.097 -> 1162 mmu set 00060000, pos 00060000 21:34:30.097 -> 1162 mmu set 00070000, pos 00070000 21:34:30.130 -> 1162 mmu set 00080000, pos 00080000 21:34:30.130 -> 1162 mmu set 00090000, pos 00090000 21:34:30.130 -> 1162 mmu set 000a0000, pos 000a0000 21:34:30.130 -> 1162 mmu set 000b0000, pos 000b0000 21:34:30.166 -> 1162 mmu set 000c0000, pos 000c0000 21:34:30.166 -> 1162 mmu set 000d0000, pos 000d0000 21:34:30.166 -> 1162 mmu set 000e0000, pos 000e0000 21:34:30.199 -> 1162 mmu set 000f0000, pos 000f0000 21:34:30.199 -> 1162 mmu set 00100000, pos 00100000 21:34:30.199 -> 1162 mmu set 00110000, pos 00110000 21:34:30.199 -> 1162 mmu set 00120000, pos 00120000 21:34:30.234 -> 1162 mmu set 00130000, pos 00130000 21:34:30.234 -> 1162 mmu set 00140000, pos 00140000 21:34:30.234 -> 1162 mmu set 00150000, pos 00150000 21:34:30.267 -> 1162 mmu set 00160000, pos 00160000 21:34:30.267 -> 1162 mmu set 00170000, pos 00170000 21:34:30.267 -> 1162 mmu set 00180000, pos 00180000 21:34:30.267 -> 1162 mmu set 00190000, pos 00190000 21:34:30.300 -> 1162 mmu set 001a0000, pos 001a0000 21:34:30.300 -> 1162 mmu set 001b0000, pos 001b0000 21:34:30.300 -> 1162 mmu set 001c0000, pos 001c0000 21:34:30.334 -> 1162 mmu set 001d0000, pos 001d0000 21:34:30.334 -> 1162 mmu set 001e0000, pos 001e0000 21:34:30.334 -> 1162 mmu set 001f0000, pos 001f0000 21:34:30.334 -> ets Jun 8 2016 00:22:57 21:34:30.334 -> 21:34:30.334 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:30.367 -> configsip: 0, SPIWP:0xee 21:34:30.367 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:30.367 -> mode:DIO, clock div:1 21:34:30.367 -> load:0x3fff0018,len:4 21:34:30.367 -> load:0x3fff001c,len:1216 21:34:30.367 -> ho 0 tail 12 room 4 21:34:30.367 -> load:0x40078000,len:10944 21:34:30.367 -> load:0x00080000,len:4340 21:34:30.674 -> ets Jun 8 2016 00:22:57 21:34:30.674 -> 21:34:30.674 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:30.674 -> configsip: 0, SPIWP:0xee 21:34:30.674 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:30.674 -> mode:DIO, clock div:1 21:34:30.710 -> load:0x3fff0018,len:4 21:34:30.710 -> load:0x3fff001c,len:1216 21:34:30.710 -> ho 0 tail 12 room 4 21:34:30.710 -> load:0x40078000,len:10944 21:34:30.710 -> load:0x00080000,len:4340 21:34:30.983 -> ets Jun 8 2016 00:22:57 21:34:31.017 -> 21:34:31.017 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:31.017 -> configsip: 0, SPIWP:0xee 21:34:31.017 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:31.017 -> mode:DIO, clock div:1 21:34:31.017 -> load:0x3fff0018,len:4 21:34:31.017 -> load:0x3fff001c,len:1216 21:34:31.017 -> ho 0 tail 12 room 4 21:34:31.017 -> load:0x40078000,len:10944 21:34:31.017 -> load:0x00080000,len:4340 21:34:31.319 -> ets Jun 8 2016 00:22:57 21:34:31.319 -> 21:34:31.319 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:31.319 -> configsip: 0, SPIWP:0xee 21:34:31.319 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:31.353 -> mode:DIO, clock div:1 21:34:31.353 -> load:0x3fff0018,len:4 21:34:31.353 -> load:0x3fff001c,len:1216 21:34:31.353 -> ho 0 tail 12 room 4 21:34:31.353 -> load:0x40078000,len:10944 21:34:31.353 -> load:0x00080000,len:4340 21:34:31.632 -> ets Jun 8 2016 00:22:57 21:34:31.665 -> 21:34:31.665 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:31.665 -> configsip: 0, SPIWP:0xee 21:34:31.665 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:31.665 -> mode:DIO, clock div:1 21:34:31.665 -> load:0x3fff0018,len:4 21:34:31.665 -> load:0x3fff001c,len:1216 21:34:31.665 -> ho 0 tail 12 room 4 21:34:31.665 -> load:0x40078000,len:10944 21:34:31.665 -> load:0x00080000,len:4340 21:34:31.982 -> ets Jun 8 2016 00:22:57 21:34:31.982 -> 21:34:31.982 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:31.982 -> configsip: 0, SPIWP:0xee 21:34:31.982 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:31.982 -> mode:DIO, clock div:1 21:34:31.982 -> load:0x3fff0018,len:4 21:34:31.982 -> load:0x3fff001c,len:1216 21:34:31.982 -> ho 0 tail 12 room 4 21:34:31.982 -> load:0x40078000,len:10944 21:34:32.016 -> load:0x00080000,len:4340 21:34:32.299 -> ets Jun 8 2016 00:22:57 21:34:32.299 -> 21:34:32.299 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:32.299 -> configsip: 0, SPIWP:0xee 21:34:32.299 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:32.299 -> mode:DIO, clock div:1 21:34:32.332 -> load:0x3fff0018,len:4 21:34:32.332 -> load:0x3fff001c,len:1216 21:34:32.332 -> ho 0 tail 12 room 4 21:34:32.332 -> load:0x40078000,len:10944 21:34:32.332 -> load:0x00080000,len:4340 21:34:32.636 -> ets Jun 8 2016 00:22:57 21:34:32.636 -> 21:34:32.636 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:32.636 -> configsip: 0, SPIWP:0xee 21:34:32.636 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:32.636 -> mode:DIO, clock div:1 21:34:32.636 -> load:0x3fff0018,len:4 21:34:32.636 -> load:0x3fff001c,len:1216 21:34:32.636 -> ho 0 tail 12 room 4 21:34:32.636 -> load:0x40078000,len:10944 21:34:32.636 -> load:0x40080000,len:4340 21:34:32.669 -> csum err:0x5f!=0x40 21:34:32.669 -> ets_main.c 371 21:34:32.805 -> ets Jun 8 2016 00:22:57 21:34:32.805 -> 21:34:32.805 -> rst:0x10 (RTCWDT_RTC_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:32.805 -> configsip: 0, SPIWP:0xee 21:34:32.805 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:32.805 -> mode:DIO, clock div:1 21:34:32.805 -> load:0x3fff0018,len:4 21:34:32.805 -> load:0x3fff001c,len:1216 21:34:32.805 -> ho 0 tail 12 room 4 21:34:32.805 -> load:0x40078000,len:10944 21:34:32.805 -> load:0x40080400,len:6388 21:34:32.805 -> entry 0x400806b4 21:34:32.838 -> ets Jun 8 2016 00:22:57 21:34:32.838 -> 21:34:32.838 -> rst:0x3 (SW_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:32.838 -> configsip: 0, SPIWP:0xee 21:34:32.838 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:32.838 -> mode:DIO, clock div:1 21:34:32.838 -> load:0x3fff0018,len:4 21:34:32.838 -> load:0x3fff001c,len:1216 21:34:32.838 -> ho 0 tail 12 room 4 21:34:32.838 -> load:0x40078000,len:10944 21:34:32.838 -> load:0x40080000,len:4340 21:34:32.838 -> csum err:0xea!=0x40 21:34:32.838 -> ets_main.c 371 21:34:33.144 -> ets Jun 8 2016 00:22:57 21:34:33.144 -> 21:34:33.144 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:33.144 -> configsip: 0, SPIWP:0xee 21:34:33.144 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:33.181 -> mode:DIO, clock div:1 21:34:33.181 -> load:0x3fff0018,len:4 21:34:33.181 -> load:0x3fff001c,len:1216 21:34:33.181 -> ho 0 tail 12 room 4 21:34:33.181 -> load:0x40078000,len:10944 21:34:33.181 -> load:0x00080000,len:4340 21:34:33.492 -> ets Jun 8 2016 00:22:57 21:34:33.492 -> 21:34:33.492 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:33.492 -> configsip: 0, SPIWP:0xee 21:34:33.492 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:33.492 -> mode:DIO, clock div:1 21:34:33.492 -> load:0x3fff0018,len:4 21:34:33.492 -> load:0x3fff001c,len:1216 21:34:33.492 -> ho 0 tail 12 room 4 21:34:33.492 -> load:0x40078000,len:10944 21:34:33.492 -> load:0x00080000,len:4340 21:34:33.803 -> ets Jun 8 2016 00:22:57 21:34:33.803 -> 21:34:33.803 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:33.803 -> configsip: 0, SPIWP:0xee 21:34:33.803 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:33.803 -> mode:DIO, clock div:1 21:34:33.803 -> load:0x3fff0018,len:4 21:34:33.803 -> load:0x3fff001c,len:1216 21:34:33.838 -> ho 0 tail 12 room 4 21:34:33.838 -> load:0x40078000,len:10944 21:34:33.838 -> load:0x00080000,len:4340 21:34:34.114 -> ets Jun 8 2016 00:22:57 21:34:34.114 -> 21:34:34.114 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:34.114 -> configsip: 0, SPIWP:0xee 21:34:34.148 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:34.148 -> mode:DIO, clock div:1 21:34:34.148 -> load:0x3fff0018,len:4 21:34:34.148 -> load:0x3fff001c,len:192 21:34:34.148 -> ho 0 tail 12 room 4 21:34:34.148 -> load:0x725f4074,len:879902836 21:34:34.148 -> 1162 mmu set 00010000, pos 00010000 21:34:34.148 -> 1162 mmu set 00020000, pos 00020000 21:34:34.184 -> 1162 mmu set 00030000, pos 00030000 21:34:34.184 -> 1162 mmu set 00040000, pos 00040000 21:34:34.184 -> 1162 mmu set 00050000, pos 00050000 21:34:34.184 -> 1162 mmu set 00060000, pos 00060000 21:34:34.222 -> 1162 mmu set 00070000, pos 00070000 21:34:34.222 -> 1162 mmu set 00080000, pos 00080000 21:34:34.222 -> 1162 mmu set 00090000, pos 00090000 21:34:34.222 -> 1162 mmu set 000a0000, pos 000a0000 21:34:34.252 -> 1162 mmu set 000b0000, pos 000b0000 21:34:34.252 -> 1162 mmu set 000c0000, pos 000c0000 21:34:34.252 -> 1162 mmu set 000d0000, pos 000d0000 21:34:34.285 -> 1162 mmu set 000e0000, pos 000e0000 21:34:34.285 -> 1162 mmu set 000f0000, pos 000f0000 21:34:34.285 -> 1162 mmu set 00100000, pos 00100000 21:34:34.285 -> 1162 mmu set 00110000, pos 00110000 21:34:34.321 -> 1162 mmu set 00120000, pos 00120000 21:34:34.321 -> 1162 mmu set 00130000, pos 00130000 21:34:34.321 -> 1162 mmu set 00140000, pos 00140000 21:34:34.355 -> 1162 mmu set 00150000, pos 00150000 21:34:34.355 -> 1162 mmu set 00160000, pos 00160000 21:34:34.355 -> 1162 mmu set 00170000, pos 00170000 21:34:34.355 -> 1162 mmu set 00180000, pos 00180000 21:34:34.388 -> 1162 mmu set 00190000, pos 00190000 21:34:34.388 -> 1162 mmu set 001a0000, pos 001a0000 21:34:34.388 -> 1162 mmu set 001b0000, pos 001b0000 21:34:34.422 -> 1162 mmu set 001c0000, pos 001c0000 21:34:34.422 -> 1162 mmu set 001d0000, pos 001d0000 21:34:34.422 -> 1162 mmu set 001e0000, pos 001e0000 21:34:34.455 -> 1162 mmu set 001f0000, pos 001f0000 21:34:34.455 -> ets Jun 8 2016 00:22:57 21:34:34.455 -> 21:34:34.455 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:34.455 -> configsip: 0, SPIWP:0xee 21:34:34.455 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:34.455 -> mode:DIO, clock div:1 21:34:34.455 -> load:0x3fff0018,len:4 21:34:34.455 -> load:0x3fff001c,len:192 21:34:34.455 -> ho 0 tail 12 room 4 21:34:34.491 -> load:0x725f4074,len:879902836 21:34:34.491 -> 1162 mmu set 00010000, pos 00010000 21:34:34.491 -> 1162 mmu set 00020000, pos 00020000 21:34:34.491 -> 1162 mmu set 00030000, pos 00030000 21:34:34.491 -> 1162 mmu set 00040000, pos 00040000 21:34:34.524 -> 1162 mmu set 00050000, pos 00050000 21:34:34.524 -> 1162 mmu set 00060000, pos 00060000 21:34:34.524 -> 1162 mmu set 00070000, pos 00070000 21:34:34.524 -> 1162 mmu set 00080000, pos 00080000 21:34:34.557 -> 1162 mmu set 00090000, pos 00090000 21:34:34.557 -> 1162 mmu set 000a0000, pos 000a0000 21:34:34.557 -> 1162 mmu set 000b0000, pos 000b0000 21:34:34.591 -> 1162 mmu set 000c0000, pos 000c0000 21:34:34.591 -> 1162 mmu set 000d0000, pos 000d0000 21:34:34.591 -> 1162 mmu set 000e0000, pos 000e0000 21:34:34.627 -> 1162 mmu set 000f0000, pos 000f0000 21:34:34.627 -> 1162 mmu set 00100000, pos 00100000 21:34:34.627 -> 1162 mmu set 00110000, pos 00110000 21:34:34.627 -> 1162 mmu set 00120000, pos 00120000 21:34:34.665 -> 1162 mmu set 00130000, pos 00130000 21:34:34.665 -> 1162 mmu set 00140000, pos 00140000 21:34:34.665 -> 1162 mmu set 00150000, pos 00150000 21:34:34.665 -> 1162 mmu set 00160000, pos 00160000 21:34:34.698 -> 1162 mmu set 00170000, pos 00170000 21:34:34.698 -> 1162 mmu set 00180000, pos 00180000 21:34:34.698 -> 1162 mmu set 00190000, pos 00190000 21:34:34.731 -> 1162 mmu set 001a0000, pos 001a0000 21:34:34.731 -> 1162 mmu set 001b0000, pos 001b0000 21:34:34.731 -> 1162 mmu set 001c0000, pos 001c0000 21:34:34.731 -> 1162 mmu set 001d0000, pos 001d0000 21:34:34.765 -> 1162 mmu set 001e0000, pos 001e0000 21:34:34.765 -> 1162 mmu set 001f0000, pos 001f0000 21:34:34.765 -> ets Jun 8 2016 00:22:57 21:34:34.765 -> 21:34:34.765 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:34.765 -> configsip: 0, SPIWP:0xee 21:34:34.799 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:34.799 -> mode:DIO, clock div:1 21:34:34.799 -> load:0x3fff0018,len:4 21:34:34.799 -> load:0x3fff001c,len:192 21:34:34.799 -> ho 0 tail 12 room 4 21:34:34.799 -> load:0x725f4074,len:879902836 21:34:34.799 -> 1162 mmu set 00010000, pos 00010000 21:34:34.799 -> 1162 mmu set 00020000, pos 00020000 21:34:34.832 -> 1162 mmu set 00030000, pos 00030000 21:34:34.832 -> 1162 mmu set 00040000, pos 00040000 21:34:34.832 -> 1162 mmu set 00050000, pos 00050000 21:34:34.832 -> 1162 mmu set 00060000, pos 00060000 21:34:34.866 -> 1162 mmu set 00070000, pos 00070000 21:34:34.866 -> 1162 mmu set 00080000, pos 00080000 21:34:34.866 -> 1162 mmu set 00090000, pos 00090000 21:34:34.899 -> 1162 mmu set 000a0000, pos 000a0000 21:34:34.899 -> 1162 mmu set 000b0000, pos 000b0000 21:34:34.899 -> 1162 mmu set 000c0000, pos 000c0000 21:34:34.935 -> 1162 mmu set 000d0000, pos 000d0000 21:34:34.935 -> 1162 mmu set 000e0000, pos 000e0000 21:34:34.935 -> 1162 mmu set 000f0000, pos 000f0000 21:34:34.935 -> 1162 mmu set 00100000, pos 00100000 21:34:34.968 -> 1162 mmu set 00110000, pos 00110000 21:34:34.968 -> 1162 mmu set 00120000, pos 00120000 21:34:34.968 -> 1162 mmu set 00130000, pos 00130000 21:34:34.968 -> 1162 mmu set 00140000, pos 00140000 21:34:35.004 -> 1162 mmu set 00150000, pos 00150000 21:34:35.004 -> 1162 mmu set 00160000, pos 00160000 21:34:35.004 -> 1162 mmu set 00170000, pos 00170000 21:34:35.004 -> 1162 mmu set 00180000, pos 00180000 21:34:35.037 -> 1162 mmu set 00190000, pos 00190000 21:34:35.037 -> 1162 mmu set 001a0000, pos 001a0000 21:34:35.037 -> 1162 mmu set 001b0000, pos 001b0000 21:34:35.071 -> 1162 mmu set 001c0000, pos 001c0000 21:34:35.071 -> 1162 mmu set 001d0000, pos 001d0000 21:34:35.071 -> 1162 mmu set 001e0000, pos 001e0000 21:34:35.104 -> 1162 mmu set 001f0000, pos 001f0000 21:34:35.104 -> ets Jun 8 2016 00:22:57 21:34:35.104 -> 21:34:35.104 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:35.104 -> configsip: 0, SPIWP:0xee 21:34:35.104 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:35.104 -> mode:DIO, clock div:1 21:34:35.104 -> load:0x3fff0018,len:4 21:34:35.104 -> load:0x3fff001c,len:192 21:34:35.104 -> ho 0 tail 12 room 4 21:34:35.138 -> load:0x725f4074,len:879902836 21:34:35.138 -> 1162 mmu set 00010000, pos 00010000 21:34:35.138 -> 1162 mmu set 00020000, pos 00020000 21:34:35.138 -> 1162 mmu set 00030000, pos 00030000 21:34:35.138 -> 1162 mmu set 00040000, pos 00040000 21:34:35.171 -> 1162 mmu set 00050000, pos 00050000 21:34:35.171 -> 1162 mmu set 00060000, pos 00060000 21:34:35.171 -> 1162 mmu set 00070000, pos 00070000 21:34:35.205 -> 1162 mmu set 00080000, pos 00080000 21:34:35.205 -> 1162 mmu set 00090000, pos 00090000 21:34:35.205 -> 1162 mmu set 000a0000, pos 000a0000 21:34:35.205 -> 1162 mmu set 000b0000, pos 000b0000 21:34:35.241 -> 1162 mmu set 000c0000, pos 000c0000 21:34:35.241 -> 1162 mmu set 000d0000, pos 000d0000 21:34:35.241 -> 1162 mmu set 000e0000, pos 000e0000 21:34:35.275 -> 1162 mmu set 000f0000, pos 000f0000 21:34:35.275 -> 1162 mmu set 00100000, pos 00100000 21:34:35.275 -> 1162 mmu set 00110000, pos 00110000 21:34:35.275 -> 1162 mmu set 00120000, pos 00120000 21:34:35.309 -> 1162 mmu set 00130000, pos 00130000 21:34:35.309 -> 1162 mmu set 00140000, pos 00140000 21:34:35.309 -> 1162 mmu set 00150000, pos 00150000 21:34:35.342 -> 1162 mmu set 00160000, pos 00160000 21:34:35.342 -> 1162 mmu set 00170000, pos 00170000 21:34:35.342 -> 1162 mmu set 00180000, pos 00180000 21:34:35.342 -> 1162 mmu set 00190000, pos 00190000 21:34:35.375 -> 1162 mmu set 001a0000, pos 001a0000 21:34:35.375 -> 1162 mmu set 001b0000, pos 001b0000 21:34:35.375 -> 1162 mmu set 001c0000, pos 001c0000 21:34:35.408 -> 1162 mmu set 001d0000, pos 001d0000 21:34:35.408 -> 1162 mmu set 001e0000, pos 001e0000 21:34:35.408 -> 1162 mmu set 001f0000, pos 001f0000 21:34:35.408 -> ets Jun 8 2016 00:22:57 21:34:35.441 -> 21:34:35.441 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:35.441 -> configsip: 0, SPIWP:0xee 21:34:35.441 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:35.441 -> mode:DIO, clock div:1 21:34:35.441 -> load:0x3fff0018,len:4 21:34:35.441 -> load:0x3fff001c,len:192 21:34:35.441 -> ho 0 tail 12 room 4 21:34:35.441 -> load:0x725f0074,len:879886452 21:34:35.441 -> 1162 mmu set 00010000, pos 00010000 21:34:35.441 -> 1162 mmu set 00020000, pos 00020000 21:34:35.474 -> 1162 mmu set 00030000, pos 00030000 21:34:35.474 -> 1162 mmu set 00040000, pos 00040000 21:34:35.474 -> 1162 mmu set 00050000, pos 00050000 21:34:35.510 -> 1162 mmu set 00060000, pos 00060000 21:34:35.510 -> 1162 mmu set 00070000, pos 00070000 21:34:35.510 -> 1162 mmu set 00080000, pos 00080000 21:34:35.510 -> 1162 mmu set 00090000, pos 00090000 21:34:35.543 -> 1162 mmu set 000a0000, pos 000a0000 21:34:35.543 -> 1162 mmu set 000b0000, pos 000b0000 21:34:35.543 -> 1162 mmu set 000c0000, pos 000c0000 21:34:35.577 -> 1162 mmu set 000d0000, pos 000d0000 21:34:35.577 -> 1162 mmu set 000e0000, pos 000e0000 21:34:35.577 -> 1162 mmu set 000f0000, pos 000f0000 21:34:35.577 -> 1162 mmu set 00100000, pos 00100000 21:34:35.610 -> 1162 mmu set 00110000, pos 00110000 21:34:35.610 -> 1162 mmu set 00120000, pos 00120000 21:34:35.610 -> 1162 mmu set 00130000, pos 00130000 21:34:35.647 -> 1162 mmu set 00140000, pos 00140000 21:34:35.647 -> 1162 mmu set 00150000, pos 00150000 21:34:35.647 -> 1162 mmu set 00160000, pos 00160000 21:34:35.647 -> 1162 mmu set 00170000, pos 00170000 21:34:35.680 -> 1162 mmu set 00180000, pos 00180000 21:34:35.680 -> 1162 mmu set 00190000, pos 00190000 21:34:35.680 -> 1162 mmu set 001a0000, pos 001a0000 21:34:35.714 -> 1162 mmu set 001b0000, pos 001b0000 21:34:35.714 -> 1162 mmu set 001c0000, pos 001c0000 21:34:35.714 -> 1162 mmu set 001d0000, pos 001d0000 21:34:35.714 -> 1162 mmu set 001e0000, pos 001e0000 21:34:35.748 -> 1162 mmu set 001f0000, pos 001f0000 21:34:35.748 -> ets Jun 8 2016 00:22:57 21:34:35.748 -> 21:34:35.748 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:35.748 -> configsip: 0, SPIWP:0xee 21:34:35.748 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:35.781 -> mode:DIO, clock div:1 21:34:35.781 -> load:0x3fff0018,len:4 21:34:35.781 -> load:0x3fff001c,len:192 21:34:35.781 -> ho 0 tail 12 room 4 21:34:35.781 -> load:0x725f0074,len:879886452 21:34:35.781 -> 1162 mmu set 00010000, pos 00010000 21:34:35.781 -> 1162 mmu set 00020000, pos 00020000 21:34:35.781 -> 1162 mmu set 00030000, pos 00030000 21:34:35.814 -> 1162 mmu set 00040000, pos 00040000 21:34:35.814 -> 1162 mmu set 00050000, pos 00050000 21:34:35.814 -> 1162 mmu set 00060000, pos 00060000 21:34:35.814 -> 1162 mmu set 00070000, pos 00070000 21:34:35.850 -> 1162 mmu set 00080000, pos 00080000 21:34:35.850 -> 1162 mmu set 00090000, pos 00090000 21:34:35.850 -> 1162 mmu set 000a0000, pos 000a0000 21:34:35.884 -> 1162 mmu set 000b0000, pos 000b0000 21:34:35.884 -> 1162 mmu set 000c0000, pos 000c0000 21:34:35.884 -> 1162 mmu set 000d0000, pos 000d0000 21:34:35.884 -> 1162 mmu set 000e0000, pos 000e0000 21:34:35.918 -> 1162 mmu set 000f0000, pos 000f0000 21:34:35.918 -> 1162 mmu set 00100000, pos 00100000 21:34:35.918 -> 1162 mmu set 00110000, pos 00110000 21:34:35.952 -> 1162 mmu set 00120000, pos 00120000 21:34:35.952 -> 1162 mmu set 00130000, pos 00130000 21:34:35.952 -> 1162 mmu set 00140000, pos 00140000 21:34:35.952 -> 1162 mmu set 00150000, pos 00150000 21:34:35.986 -> 1162 mmu set 00160000, pos 00160000 21:34:35.986 -> 1162 mmu set 00170000, pos 00170000 21:34:35.986 -> 1162 mmu set 00180000, pos 00180000 21:34:36.020 -> 1162 mmu set 00190000, pos 00190000 21:34:36.020 -> 1162 mmu set 001a0000, pos 001a0000 21:34:36.020 -> 1162 mmu set 001b0000, pos 001b0000 21:34:36.020 -> 1162 mmu set 001c0000, pos 001c0000 21:34:36.053 -> 1162 mmu set 001d0000, pos 001d0000 21:34:36.053 -> 1162 mmu set 001e0000, pos 001e0000 21:34:36.053 -> 1162 mmu set 001f0000, pos 001f0000 21:34:36.086 -> ets Jun 8 2016 00:22:57 21:34:36.086 -> 21:34:36.086 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:36.086 -> configsip: 0, SPIWP:0xee 21:34:36.086 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:36.086 -> mode:DIO, clock div:1 21:34:36.086 -> load:0x3fff0018,len:4 21:34:36.086 -> load:0x3fff001c,len:192 21:34:36.086 -> ho 0 tail 12 room 4 21:34:36.086 -> load:0x725f0074,len:879886452 21:34:36.086 -> 1162 mmu set 00010000, pos 00010000 21:34:36.119 -> 1162 mmu set 00020000, pos 00020000 21:34:36.119 -> 1162 mmu set 00030000, pos 00030000 21:34:36.119 -> 1162 mmu set 00040000, pos 00040000 21:34:36.154 -> 1162 mmu set 00050000, pos 00050000 21:34:36.154 -> 1162 mmu set 00060000, pos 00060000 21:34:36.154 -> 1162 mmu set 00070000, pos 00070000 21:34:36.154 -> 1162 mmu set 00080000, pos 00080000 21:34:36.191 -> 1162 mmu set 00090000, pos 00090000 21:34:36.191 -> 1162 mmu set 000a0000, pos 000a0000 21:34:36.191 -> 1162 mmu set 000b0000, pos 000b0000 21:34:36.191 -> 1162 mmu set 000c0000, pos 000c0000 21:34:36.224 -> 1162 mmu set 000d0000, pos 000d0000 21:34:36.224 -> 1162 mmu set 000e0000, pos 000e0000 21:34:36.224 -> 1162 mmu set 000f0000, pos 000f0000 21:34:36.258 -> 1162 mmu set 00100000, pos 00100000 21:34:36.258 -> 1162 mmu set 00110000, pos 00110000 21:34:36.258 -> 1162 mmu set 00120000, pos 00120000 21:34:36.258 -> 1162 mmu set 00130000, pos 00130000 21:34:36.291 -> 1162 mmu set 00140000, pos 00140000 21:34:36.291 -> 1162 mmu set 00150000, pos 00150000 21:34:36.291 -> 1162 mmu set 00160000, pos 00160000 21:34:36.324 -> 1162 mmu set 00170000, pos 00170000 21:34:36.324 -> 1162 mmu set 00180000, pos 00180000 21:34:36.324 -> 1162 mmu set 00190000, pos 00190000 21:34:36.324 -> 1162 mmu set 001a0000, pos 001a0000 21:34:36.358 -> 1162 mmu set 001b0000, pos 001b0000 21:34:36.358 -> 1162 mmu set 001c0000, pos 001c0000 21:34:36.358 -> 1162 mmu set 001d0000, pos 001d0000 21:34:36.391 -> 1162 mmu set 001e0000, pos 001e0000 21:34:36.391 -> 1162 mmu set 001f0000, pos 001f0000 21:34:36.391 -> ets Jun 8 2016 00:22:57 21:34:36.391 -> 21:34:36.391 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:36.391 -> configsip: 0, SPIWP:0xee 21:34:36.424 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:36.424 -> mode:DIO, clock div:1 21:34:36.424 -> load:0x3fff0018,len:4 21:34:36.424 -> load:0x3fff001c,len:192 21:34:36.424 -> ho 0 tail 12 room 4 21:34:36.424 -> load:0x725f0074,len:879886452 21:34:36.424 -> 1162 mmu set 00010000, pos 00010000 21:34:36.424 -> 1162 mmu set 00020000, pos 00020000 21:34:36.462 -> 1162 mmu set 00030000, pos 00030000 21:34:36.462 -> 1162 mmu set 00040000, pos 00040000 21:34:36.462 -> 1162 mmu set 00050000, pos 00050000 21:34:36.462 -> 1162 mmu set 00060000, pos 00060000 21:34:36.498 -> 1162 mmu set 00070000, pos 00070000 21:34:36.498 -> 1162 mmu set 00080000, pos 00080000 21:34:36.498 -> 1162 mmu set 00090000, pos 00090000 21:34:36.498 -> 1162 mmu set 000a0000, pos 000a0000 21:34:36.532 -> 1162 mmu set 000b0000, pos 000b0000 21:34:36.532 -> 1162 mmu set 000c0000, pos 000c0000 21:34:36.532 -> 1162 mmu set 000d0000, pos 000d0000 21:34:36.532 -> 1162 mmu set 000e0000, pos 000e0000 21:34:36.566 -> 1162 mmu set 000f0000, pos 000f0000 21:34:36.566 -> 1162 mmu set 00100000, pos 00100000 21:34:36.566 -> 1162 mmu set 00110000, pos 00110000 21:34:36.599 -> 1162 mmu set 00120000, pos 00120000 21:34:36.599 -> 1162 mmu set 00130000, pos 00130000 21:34:36.599 -> 1162 mmu set 00140000, pos 00140000 21:34:36.632 -> 1162 mmu set 00150000, pos 00150000 21:34:36.632 -> 1162 mmu set 00160000, pos 00160000 21:34:36.632 -> 1162 mmu set 00170000, pos 00170000 21:34:36.632 -> 1162 mmu set 00180000, pos 00180000 21:34:36.666 -> 1162 mmu set 00190000, pos 00190000 21:34:36.666 -> 1162 mmu set 001a0000, pos 001a0000 21:34:36.666 -> 1162 mmu set 001b0000, pos 001b0000 21:34:36.702 -> 1162 mmu set 001c0000, pos 001c0000 21:34:36.702 -> 1162 mmu set 001d0000, pos 001d0000 21:34:36.702 -> 1162 mmu set 001e0000, pos 001e0000 21:34:36.702 -> 1162 mmu set 001f0000, pos 001f0000 21:34:36.736 -> ets Jun 8 2016 00:22:57 21:34:36.736 -> 21:34:36.736 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:36.736 -> configsip: 0, SPIWP:0xee 21:34:36.736 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:36.736 -> mode:DIO, clock div:1 21:34:36.736 -> load:0x3fff0018,len:4 21:34:36.736 -> load:0x3fff001c,len:192 21:34:36.736 -> ho 0 tail 12 room 4 21:34:36.736 -> load:0x725f0074,len:879886452 21:34:36.736 -> 1162 mmu set 00010000, pos 00010000 21:34:36.770 -> 1162 mmu set 00020000, pos 00020000 21:34:36.770 -> 1162 mmu set 00030000, pos 00030000 21:34:36.770 -> 1162 mmu set 00040000, pos 00040000 21:34:36.803 -> 1162 mmu set 00050000, pos 00050000 21:34:36.803 -> 1162 mmu set 00060000, pos 00060000 21:34:36.803 -> 1162 mmu set 00070000, pos 00070000 21:34:36.803 -> 1162 mmu set 00080000, pos 00080000 21:34:36.836 -> 1162 mmu set 00090000, pos 00090000 21:34:36.836 -> 1162 mmu set 000a0000, pos 000a0000 21:34:36.836 -> 1162 mmu set 000b0000, pos 000b0000 21:34:36.871 -> 1162 mmu set 000c0000, pos 000c0000 21:34:36.871 -> 1162 mmu set 000d0000, pos 000d0000 21:34:36.871 -> 1162 mmu set 000e0000, pos 000e0000 21:34:36.871 -> 1162 mmu set 000f0000, pos 000f0000 21:34:36.905 -> 1162 mmu set 00100000, pos 00100000 21:34:36.905 -> 1162 mmu set 00110000, pos 00110000 21:34:36.905 -> 1162 mmu set 00120000, pos 00120000 21:34:36.939 -> 1162 mmu set 00130000, pos 00130000 21:34:36.939 -> 1162 mmu set 00140000, pos 00140000 21:34:36.939 -> 1162 mmu set 00150000, pos 00150000 21:34:36.939 -> 1162 mmu set 00160000, pos 00160000 21:34:36.972 -> 1162 mmu set 00170000, pos 00170000 21:34:36.972 -> 1162 mmu set 00180000, pos 00180000 21:34:36.972 -> 1162 mmu set 00190000, pos 00190000 21:34:37.005 -> 1162 mmu set 001a0000, pos 001a0000 21:34:37.005 -> 1162 mmu set 001b0000, pos 001b0000 21:34:37.005 -> 1162 mmu set 001c0000, pos 001c0000 21:34:37.005 -> 1162 mmu set 001d0000, pos 001d0000 21:34:37.038 -> 1162 mmu set 001e0000, pos 001e0000 21:34:37.038 -> 1162 mmu set 001f0000, pos 001f0000 21:34:37.038 -> ets Jun 8 2016 00:22:57 21:34:37.038 -> 21:34:37.038 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:37.072 -> configsip: 0, SPIWP:0xee 21:34:37.072 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:37.072 -> mode:DIO, clock div:1 21:34:37.072 -> load:0x3fff0018,len:4 21:34:37.072 -> load:0x3fff001c,len:192 21:34:37.072 -> ho 0 tail 12 room 4 21:34:37.072 -> load:0x725f4074,len:879902836 21:34:37.072 -> 1162 mmu set 00010000, pos 00010000 21:34:37.072 -> 1162 mmu set 00020000, pos 00020000 21:34:37.105 -> 1162 mmu set 00030000, pos 00030000 21:34:37.105 -> 1162 mmu set 00040000, pos 00040000 21:34:37.105 -> 1162 mmu set 00050000, pos 00050000 21:34:37.105 -> 1162 mmu set 00060000, pos 00060000 21:34:37.140 -> 1162 mmu set 00070000, pos 00070000 21:34:37.140 -> 1162 mmu set 00080000, pos 00080000 21:34:37.140 -> 1162 mmu set 00090000, pos 00090000 21:34:37.174 -> 1162 mmu set 000a0000, pos 000a0000 21:34:37.174 -> 1162 mmu set 000b0000, pos 000b0000 21:34:37.174 -> 1162 mmu set 000c0000, pos 000c0000 21:34:37.174 -> 1162 mmu set 000d0000, pos 000d0000 21:34:37.210 -> 1162 mmu set 000e0000, pos 000e0000 21:34:37.210 -> 1162 mmu set 000f0000, pos 000f0000 21:34:37.210 -> 1162 mmu set 00100000, pos 00100000 21:34:37.243 -> 1162 mmu set 00110000, pos 00110000 21:34:37.243 -> 1162 mmu set 00120000, pos 00120000 21:34:37.243 -> 1162 mmu set 00130000, pos 00130000 21:34:37.243 -> 1162 mmu set 00140000, pos 00140000 21:34:37.276 -> 1162 mmu set 00150000, pos 00150000 21:34:37.276 -> 1162 mmu set 00160000, pos 00160000 21:34:37.276 -> 1162 mmu set 00170000, pos 00170000 21:34:37.310 -> 1162 mmu set 00180000, pos 00180000 21:34:37.310 -> 1162 mmu set 00190000, pos 00190000 21:34:37.310 -> 1162 mmu set 001a0000, pos 001a0000 21:34:37.310 -> 1162 mmu set 001b0000, pos 001b0000 21:34:37.348 -> 1162 mmu set 001c0000, pos 001c0000 21:34:37.348 -> 1162 mmu set 001d0000, pos 001d0000 21:34:37.348 -> 1162 mmu set 001e0000, pos 001e0000 21:34:37.348 -> 1162 mmu set 001f0000, pos 001f0000 21:34:37.381 -> ets Jun 8 2016 00:22:57 21:34:37.381 -> 21:34:37.381 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:37.381 -> configsip: 0, SPIWP:0xee 21:34:37.381 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:37.381 -> mode:DIO, clock div:1 21:34:37.381 -> load:0x3fff0018,len:4 21:34:37.381 -> load:0x3fff001c,len:192 21:34:37.381 -> ho 0 tail 12 room 4 21:34:37.381 -> load:0x725f4074,len:879902836 21:34:37.414 -> 1162 mmu set 00010000, pos 00010000 21:34:37.414 -> 1162 mmu set 00020000, pos 00020000 21:34:37.414 -> 1162 mmu set 00030000, pos 00030000 21:34:37.414 -> 1162 mmu set 00040000, pos 00040000 21:34:37.448 -> 1162 mmu set 00050000, pos 00050000 21:34:37.448 -> 1162 mmu set 00060000, pos 00060000 21:34:37.448 -> 1162 mmu set 00070000, pos 00070000 21:34:37.481 -> 1162 mmu set 00080000, pos 00080000 21:34:37.481 -> 1162 mmu set 00090000, pos 00090000 21:34:37.481 -> 1162 mmu set 000a0000, pos 000a0000 21:34:37.481 -> 1162 mmu set 000b0000, pos 000b0000 21:34:37.516 -> 1162 mmu set 000c0000, pos 000c0000 21:34:37.516 -> 1162 mmu set 000d0000, pos 000d0000 21:34:37.516 -> 1162 mmu set 000e0000, pos 000e0000 21:34:37.549 -> 1162 mmu set 000f0000, pos 000f0000 21:34:37.549 -> 1162 mmu set 00100000, pos 00100000 21:34:37.549 -> 1162 mmu set 00110000, pos 00110000 21:34:37.549 -> 1162 mmu set 00120000, pos 00120000 21:34:37.584 -> 1162 mmu set 00130000, pos 00130000 21:34:37.584 -> 1162 mmu set 00140000, pos 00140000 21:34:37.584 -> 1162 mmu set 00150000, pos 00150000 21:34:37.619 -> 1162 mmu set 00160000, pos 00160000 21:34:37.619 -> 1162 mmu set 00170000, pos 00170000 21:34:37.619 -> 1162 mmu set 00180000, pos 00180000 21:34:37.619 -> 1162 mmu set 00190000, pos 00190000 21:34:37.652 -> 1162 mmu set 001a0000, pos 001a0000 21:34:37.652 -> 1162 mmu set 001b0000, pos 001b0000 21:34:37.652 -> 1162 mmu set 001c0000, pos 001c0000 21:34:37.686 -> 1162 mmu set 001d0000, pos 001d0000 21:34:37.686 -> 1162 mmu set 001e0000, pos 001e0000 21:34:37.686 -> 1162 mmu set 001f0000, pos 001f0000 21:34:37.686 -> ets Jun 8 2016 00:22:57 21:34:37.686 -> 21:34:37.686 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:37.719 -> configsip: 0, SPIWP:0xee 21:34:37.719 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:37.719 -> mode:DIO, clock div:1 21:34:37.719 -> load:0x3fff0018,len:4 21:34:37.719 -> load:0x3fff001c,len:192 21:34:37.719 -> ho 0 tail 12 room 4 21:34:37.719 -> load:0x725f0074,len:879886452 21:34:37.719 -> 1162 mmu set 00010000, pos 00010000 21:34:37.719 -> 1162 mmu set 00020000, pos 00020000 21:34:37.753 -> 1162 mmu set 00030000, pos 00030000 21:34:37.753 -> 1162 mmu set 00040000, pos 00040000 21:34:37.753 -> 1162 mmu set 00050000, pos 00050000 21:34:37.786 -> 1162 mmu set 00060000, pos 00060000 21:34:37.786 -> 1162 mmu set 00070000, pos 00070000 21:34:37.786 -> 1162 mmu set 00080000, pos 00080000 21:34:37.786 -> 1162 mmu set 00090000, pos 00090000 21:34:37.819 -> 1162 mmu set 000a0000, pos 000a0000 21:34:37.819 -> 1162 mmu set 000b0000, pos 000b0000 21:34:37.819 -> 1162 mmu set 000c0000, pos 000c0000 21:34:37.853 -> 1162 mmu set 000d0000, pos 000d0000 21:34:37.853 -> 1162 mmu set 000e0000, pos 000e0000 21:34:37.853 -> 1162 mmu set 000f0000, pos 000f0000 21:34:37.853 -> 1162 mmu set 00100000, pos 00100000 21:34:37.900 -> 1162 mmu set 00110000, pos 00110000 21:34:37.900 -> 1162 mmu set 00120000, pos 00120000 21:34:37.900 -> 1162 mmu set 00130000, pos 00130000 21:34:37.900 -> 1162 mmu set 00140000, pos 00140000 21:34:37.923 -> 1162 mmu set 00150000, pos 00150000 21:34:37.923 -> 1162 mmu set 00160000, pos 00160000 21:34:37.923 -> 1162 mmu set 00170000, pos 00170000 21:34:37.960 -> 1162 mmu set 00180000, pos 00180000 21:34:37.960 -> 1162 mmu set 00190000, pos 00190000 21:34:37.960 -> 1162 mmu set 001a0000, pos 001a0000 21:34:37.960 -> 1162 mmu set 001b0000, pos 001b0000 21:34:37.998 -> 1162 mmu set 001c0000, pos 001c0000 21:34:37.998 -> 1162 mmu set 001d0000, pos 001d0000 21:34:37.998 -> 1162 mmu set 001e0000, pos 001e0000 21:34:37.998 -> 1162 mmu set 001f0000, pos 001f0000 21:34:38.031 -> ets Jun 8 2016 00:22:57 21:34:38.031 -> 21:34:38.031 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:38.031 -> configsip: 0, SPIWP:0xee 21:34:38.031 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:38.031 -> mode:DIO, clock div:1 21:34:38.031 -> load:0x3fff0018,len:4 21:34:38.031 -> load:0x3fff001c,len:192 21:34:38.031 -> ho 0 tail 12 room 4 21:34:38.066 -> load:0x725f0074,len:879886452 21:34:38.066 -> 1162 mmu set 00010000, pos 00010000 21:34:38.066 -> 1162 mmu set 00020000, pos 00020000 21:34:38.066 -> 1162 mmu set 00030000, pos 00030000 21:34:38.066 -> 1162 mmu set 00040000, pos 00040000 21:34:38.101 -> 1162 mmu set 00050000, pos 00050000 21:34:38.101 -> 1162 mmu set 00060000, pos 00060000 21:34:38.101 -> 1162 mmu set 00070000, pos 00070000 21:34:38.101 -> 1162 mmu set 00080000, pos 00080000 21:34:38.134 -> 1162 mmu set 00090000, pos 00090000 21:34:38.134 -> 1162 mmu set 000a0000, pos 000a0000 21:34:38.134 -> 1162 mmu set 000b0000, pos 000b0000 21:34:38.168 -> 1162 mmu set 000c0000, pos 000c0000 21:34:38.168 -> 1162 mmu set 000d0000, pos 000d0000 21:34:38.168 -> 1162 mmu set 000e0000, pos 000e0000 21:34:38.168 -> 1162 mmu set 000f0000, pos 000f0000 21:34:38.205 -> 1162 mmu set 00100000, pos 00100000 21:34:38.205 -> 1162 mmu set 00110000, pos 00110000 21:34:38.205 -> 1162 mmu set 00120000, pos 00120000 21:34:38.243 -> 1162 mmu set 00130000, pos 00130000 21:34:38.243 -> 1162 mmu set 00140000, pos 00140000 21:34:38.243 -> 1162 mmu set 00150000, pos 00150000 21:34:38.243 -> 1162 mmu set 00160000, pos 00160000 21:34:38.279 -> 1162 mmu set 00170000, pos 00170000 21:34:38.279 -> 1162 mmu set 00180000, pos 00180000 21:34:38.279 -> 1162 mmu set 00190000, pos 00190000 21:34:38.279 -> 1162 mmu set 001a0000, pos 001a0000 21:34:38.314 -> 1162 mmu set 001b0000, pos 001b0000 21:34:38.314 -> 1162 mmu set 001c0000, pos 001c0000 21:34:38.314 -> 1162 mmu set 001d0000, pos 001d0000 21:34:38.314 -> 1162 mmu set 001e0000, pos 001e0000 21:34:38.348 -> 1162 mmu set 001f0000, pos 001f0000 21:34:38.348 -> ets Jun 8 2016 00:22:57 21:34:38.348 -> 21:34:38.348 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:38.348 -> configsip: 0, SPIWP:0xee 21:34:38.348 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:38.348 -> mode:DIO, clock div:1 21:34:38.381 -> load:0x3fff0018,len:4 21:34:38.381 -> load:0x3fff001c,len:192 21:34:38.381 -> ho 0 tail 12 room 4 21:34:38.381 -> load:0x725f0074,len:879886452 21:34:38.381 -> 1162 mmu set 00010000, pos 00010000 21:34:38.381 -> 1162 mmu set 00020000, pos 00020000 21:34:38.381 -> 1162 mmu set 00030000, pos 00030000 21:34:38.415 -> 1162 mmu set 00040000, pos 00040000 21:34:38.415 -> 1162 mmu set 00050000, pos 00050000 21:34:38.415 -> 1162 mmu set 00060000, pos 00060000 21:34:38.415 -> 1162 mmu set 00070000, pos 00070000 21:34:38.448 -> 1162 mmu set 00080000, pos 00080000 21:34:38.448 -> 1162 mmu set 00090000, pos 00090000 21:34:38.448 -> 1162 mmu set 000a0000, pos 000a0000 21:34:38.482 -> 1162 mmu set 000b0000, pos 000b0000 21:34:38.482 -> 1162 mmu set 000c0000, pos 000c0000 21:34:38.482 -> 1162 mmu set 000d0000, pos 000d0000 21:34:38.519 -> 1162 mmu set 000e0000, pos 000e0000 21:34:38.519 -> 1162 mmu set 000f0000, pos 000f0000 21:34:38.519 -> 1162 mmu set 00100000, pos 00100000 21:34:38.519 -> 1162 mmu set 00110000, pos 00110000 21:34:38.553 -> 1162 mmu set 00120000, pos 00120000 21:34:38.553 -> 1162 mmu set 00130000, pos 00130000 21:34:38.553 -> 1162 mmu set 00140000, pos 00140000 21:34:38.553 -> 1162 mmu set 00150000, pos 00150000 21:34:38.586 -> 1162 mmu set 00160000, pos 00160000 21:34:38.586 -> 1162 mmu set 00170000, pos 00170000 21:34:38.586 -> 1162 mmu set 00180000, pos 00180000 21:34:38.619 -> 1162 mmu set 00190000, pos 00190000 21:34:38.619 -> 1162 mmu set 001a0000, pos 001a0000 21:34:38.619 -> 1162 mmu set 001b0000, pos 001b0000 21:34:38.619 -> 1162 mmu set 001c0000, pos 001c0000 21:34:38.654 -> 1162 mmu set 001d0000, pos 001d0000 21:34:38.654 -> 1162 mmu set 001e0000, pos 001e0000 21:34:38.654 -> 1162 mmu set 001f0000, pos 001f0000 21:34:38.688 -> ets Jun 8 2016 00:22:57 21:34:38.688 -> 21:34:38.688 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:38.688 -> configsip: 0, SPIWP:0xee 21:34:38.688 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:38.688 -> mode:DIO, clock div:1 21:34:38.688 -> load:0x3fff0018,len:4 21:34:38.688 -> load:0x3fff001c,len:192 21:34:38.688 -> ho 0 tail 12 room 4 21:34:38.688 -> load:0x725f0074,len:879886452 21:34:38.688 -> 1162 mmu set 00010000, pos 00010000 21:34:38.722 -> 1162 mmu set 00020000, pos 00020000 21:34:38.722 -> 1162 mmu set 00030000, pos 00030000 21:34:38.722 -> 1162 mmu set 00040000, pos 00040000 21:34:38.722 -> 1162 mmu set 00050000, pos 00050000 21:34:38.755 -> 1162 mmu set 00060000, pos 00060000 21:34:38.755 -> 1162 mmu set 00070000, pos 00070000 21:34:38.755 -> 1162 mmu set 00080000, pos 00080000 21:34:38.789 -> 1162 mmu set 00090000, pos 00090000 21:34:38.789 -> 1162 mmu set 000a0000, pos 000a0000 21:34:38.789 -> 1162 mmu set 000b0000, pos 000b0000 21:34:38.789 -> 1162 mmu set 000c0000, pos 000c0000 21:34:38.822 -> 1162 mmu set 000d0000, pos 000d0000 21:34:38.822 -> 1162 mmu set 000e0000, pos 000e0000 21:34:38.822 -> 1162 mmu set 000f0000, pos 000f0000 21:34:38.855 -> 1162 mmu set 00100000, pos 00100000 21:34:38.855 -> 1162 mmu set 00110000, pos 00110000 21:34:38.855 -> 1162 mmu set 00120000, pos 00120000 21:34:38.889 -> 1162 mmu set 00130000, pos 00130000 21:34:38.889 -> 1162 mmu set 00140000, pos 00140000 21:34:38.889 -> 1162 mmu set 00150000, pos 00150000 21:34:38.889 -> 1162 mmu set 00160000, pos 00160000 21:34:38.923 -> 1162 mmu set 00170000, pos 00170000 21:34:38.923 -> 1162 mmu set 00180000, pos 00180000 21:34:38.923 -> 1162 mmu set 00190000, pos 00190000 21:34:38.956 -> 1162 mmu set 001a0000, pos 001a0000 21:34:38.956 -> 1162 mmu set 001b0000, pos 001b0000 21:34:38.956 -> 1162 mmu set 001c0000, pos 001c0000 21:34:38.956 -> 1162 mmu set 001d0000, pos 001d0000 21:34:38.990 -> 1162 mmu set 001e0000, pos 001e0000 21:34:38.990 -> 1162 mmu set 001f0000, pos 001f0000 21:34:38.990 -> ets Jun 8 2016 00:22:57 21:34:38.990 -> 21:34:38.990 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:38.990 -> configsip: 0, SPIWP:0xee 21:34:39.024 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:39.024 -> mode:DIO, clock div:1 21:34:39.024 -> load:0x3fff0018,len:4 21:34:39.024 -> load:0x3fff001c,len:1216 21:34:39.024 -> ho 0 tail 12 room 4 21:34:39.024 -> load:0x40078000,len:10944 21:34:39.024 -> load:0x40080000,len:6388 21:34:39.024 -> csum err:0xb9!=0xa0 21:34:39.024 -> ets_main.c 371 21:34:39.326 -> ets Jun 8 2016 00:22:57 21:34:39.326 -> 21:34:39.326 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:39.326 -> configsip: 0, SPIWP:0xee 21:34:39.326 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:39.326 -> mode:DIO, clock div:1 21:34:39.326 -> load:0x3fff0018,len:4 21:34:39.326 -> load:0x3fff001c,len:1216 21:34:39.360 -> ho 0 tail 12 room 4 21:34:39.360 -> load:0x40078000,len:10944 21:34:39.360 -> load:0x40080400,len:6388 21:34:39.360 -> csum err:0xf3!=0xa2 21:34:39.360 -> ets_main.c 371 21:34:39.632 -> ets Jun 8 2016 00:22:57 21:34:39.668 -> 21:34:39.668 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:39.668 -> configsip: 0, SPIWP:0xee 21:34:39.668 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:39.668 -> mode:DIO, clock div:1 21:34:39.668 -> load:0x3fff0018,len:4 21:34:39.668 -> load:0x3fff001c,len:1216 21:34:39.668 -> ho 0 tail 12 room 4 21:34:39.668 -> load:0x40078000,len:10944 21:34:39.668 -> load:0x40080000,len:4340 21:34:39.668 -> csum err:0xbf!=0x40 21:34:39.668 -> ets_main.c 371 21:34:39.977 -> ets Jun 8 2016 00:22:57 21:34:39.977 -> 21:34:39.977 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:39.977 -> configsip: 0, SPIWP:0xee 21:34:39.977 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:39.977 -> mode:DIO, clock div:1 21:34:39.977 -> load:0x3fff0018,len:4 21:34:39.977 -> load:0x3fff001c,len:1216 21:34:40.010 -> ho 0 tail 12 room 4 21:34:40.010 -> load:0x40078000,len:10944 21:34:40.010 -> load:0x00080000,len:4340 21:34:40.282 -> ets Jun 8 2016 00:22:57 21:34:40.315 -> 21:34:40.315 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:40.315 -> configsip: 0, SPIWP:0xee 21:34:40.315 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:40.315 -> mode:DIO, clock div:1 21:34:40.315 -> load:0x3fff0018,len:4 21:34:40.315 -> load:0x3fff001c,len:1216 21:34:40.315 -> ho 0 tail 12 room 4 21:34:40.315 -> load:0x40078000,len:10944 21:34:40.315 -> load:0x40080000,len:4340 21:34:40.315 -> csum err:0xab!=0x40 21:34:40.315 -> ets_main.c 371 21:34:40.621 -> ets Jun 8 2016 00:22:57 21:34:40.621 -> 21:34:40.621 -> rst:0x7 (TG0WDT_SYS_RESET),boot:0x13 (SPI_FAST_FLASH_BOOT) 21:34:40.621 -> configsip: 0, SPIWP:0xee 21:34:40.621 -> clk_drv:0x00,q_drv:0x00,d_drv:0x00,cs0_drv:0x00,hd_drv:0x00,wp_drv:0x00 21:34:40.655 -> mode:DIO, clock div:1 21:34:40.655 -> load:0x3fff0018,len:4 21:34:40.655 -> load:0x3fff001c,len:1216 21:34:40.655 -> ho 0 tail 12 room 4 21:34:40.655 -> load:0x40078000,len:10944 21:34:40.655 -> load:0x40080000,len:4340 21:34:40.655 -> csum err:0x2a!=0x40 21:34:40.655 -> ets_main.c 371 21:34:40.925 -> ets Jun 8 2016 00:22:57⸮ets Jun 8 2016 00:22:57 21:34:40.925 -> 21:34:40.925 -> rst⸮etsets Jun 8 2016 00:22:57 21:34:40.925 -> 21:34:40.925 -> rst:0x1 (POWERON_RESET),boot:0x3 (DOWNLOAD_BOOT(UART0/UART1/SDIO_REI_REO_V2)) 21:34:40.925 -> waiting for download